MaximumTaco
May8-04, 04:18 AM
2 inputs, A and B.
2 Outputs, X and Y.
X is high if there has been at least 1 previous clock transition where A is high, and none where B has been high.
Y is high if there has been at least 2 B=1 and at most 1 A=1 at previous positive clock transitions.
Provision must be made to reset the counts with another synchronous input.
Only D FF's and common gates must be used.
The design must be as simple and efficent as possible
Where do i begin tackling this?
2 Outputs, X and Y.
X is high if there has been at least 1 previous clock transition where A is high, and none where B has been high.
Y is high if there has been at least 2 B=1 and at most 1 A=1 at previous positive clock transitions.
Provision must be made to reset the counts with another synchronous input.
Only D FF's and common gates must be used.
The design must be as simple and efficent as possible
Where do i begin tackling this?