Can the logical state really be determined during this time?

[JamesJames]

Using a 555 timer (square wave input) as a NOT gate, can the logical state (0 or 1) be determined during rise and fall times? I would think that this is some kind of discontinuity during which the properties of the wave are not known but am not very sure about the logical state thing. It is high prior to the falling edge and then "jumps" to low. Do all oscilloscopes account for this logical state determination?

James

 

[JamesJames]

Anyone? I; m a bit confused about this subject to say the least. It would really help if I could get some clarification.

 

[berkeman]

Using a 555 timer (square wave input) as a NOT gate, can the logical state (0 or 1) be determined during rise and fall times? I would think that this is some kind of discontinuity during which the properties of the wave are not known but am not very sure about the logical state thing. It is high prior to the falling edge and then "jumps" to low. Do all oscilloscopes account for this logical state determination?
James

I don't understand the reference to using a 555 timer as a NOT gate, but I'll try to answer what I think you're asking about. When you observe a signal on an oscilloscope, you are seeing the true analog waveform. You adjust the V/div on the vertical and the t/div on the horizontal, and you adjust the vertical voltage offset and the horizontal time delay, in order to best look at your signal. With an oscilloscope, you see everything about the waveform.

With a logic analyzer of other digital probe, the signal is simplified to logic levels like 1 and 0. To do this, the instrument has to know what the Vih and Vil voltage levels should be, or at least what the dividing line is between a high and low logic level. On the HP 16500 logic analyzer that I use in my work, for example, you can choose to use "TTL" logic trip levels, or you can set your own special threshold voltage (which I do when I'm working with 3.3V logic, for example).

A further consideration is that digital logic gates are generally not designed to handle analog waveforms at their inputs. That is, the input signals expected by digital logic should ramp quickly from low to high or high to low, and not spend much time in the middle voltage range. Typical digital logic will ramp in a few nanoseconds (ns). If you put a slowly varying signal into the input of a digital logic gate, when the input voltage is in the middle part of the voltage range, the digital logic gate will draw a larger Icc than normal, and may oscillate under some conditions. If you need to put an analog signal into a digital logic gate (like if you are making a simple relaxation oscillator), you will need to use a Schottky input gate, which has explicit hysteresis feedback in its input stage.