Most efficient logic for 10 bit decoder

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SUMMARY

The discussion focuses on implementing a 10-bit decoder that efficiently translates 10 input lines into one of 1024 output lines. A systematic approach is recommended, utilizing two three-to-eight decoders and a four-to-sixteen line demultiplexer, followed by 1024 three-input NAND gates. Considerations include fanout, propagation delay, and capacitance, particularly when using TTL versus CMOS technology. For distributed systems, the use of multiple decoders across several cards is advised to manage signal integrity and reduce complexity.

PREREQUISITES
  • Understanding of digital logic design, specifically decoders and multiplexers.
  • Familiarity with CMOS and TTL technologies and their characteristics.
  • Knowledge of fanout and propagation delay in digital circuits.
  • Experience with programmable logic devices for circuit implementation.
NEXT STEPS
  • Research the design and implementation of three-to-eight decoders.
  • Learn about four-to-sixteen line demultiplexers and their applications.
  • Explore the characteristics and differences between CMOS and TTL technologies.
  • Investigate programmable logic devices and their use in complex digital circuits.
USEFUL FOR

Digital circuit designers, embedded systems engineers, and anyone involved in the design of large-scale decoder systems or memory arrays.

bsun2
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Hello,
What is a good way to implement the logic for a 10 bit (10 to 1024) decoder? A method that is systematic, has low fanout, fanin, propagation delay, and capacitance is desired. It would be helpful if you could find some websites that implement this design.

Thanks,
James
 
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To be sure, what are you looking for? An A to D converter, for example, or the logic to take a ten-line input and from it, select and enable one of 1024 output lines (that's awfully big)? If it's the latter, you can (simply) take two three-to-eight decoders, and a four-to-sixteen line demux, and feed the proper outputs of these to 1024 three-input NANDs (that's an awful lot of NANDs). For a distributed system, that wouldn't be too bad, but I don't think you'd want to derive that many signals in one place.

As an alternative, if it's distributed (for example, on thirty two cards, each putting out thirty two lines) you could, for example, put two four-to-sixteen line decoders on each, and include the proper select logic for each of the decoders.

Fan-out for the for the ten signal drive lines would be a consideration. Each of the four low-order lines would have to drive sixty four decoder inputs (possibly OK for CMOS, but I wouldn't want to try that directly with TTL; buffering would be needed - - probably at the both - input to each of the daughter boards and the output from the main board). This, by the way, is the type of problem typically encountered when designing memory arrays.

If it all has to be done from a single board or module, you might look to using some form of programmable logic.

KM
 
Another driving factor, is what do you intend to do with the output lines? If it is to drive something like a set of commands (on/off, etc.) or to enable sampling inputs (telemetry, etc.), considerations like those above are OK. If, however it is to drive something like a scanned LED display, etc., additional simplification might be possible.

KM
 

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