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Paper presentation(Electronics and telecommunication engineering)

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arvik
#1
Mar3-08, 12:08 PM
P: 6
Hi there,
As u might have understood I am an Electronics and telecommunication engineering student.I am hoping to participate in some of the technical paper presentation competitions in my area.I wanted some suggestions for the topic I might choose.The topic should be from my field and if possible it should be related to new developments in the field of electronics or tele-communication.
Thanks in advance.
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berkeman
#2
Mar5-08, 09:18 AM
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Welcome to the PF, arvik. What are your thoughts so far? What topics seem interesting to you? What areas of telecommunications are you studying?

Certainly the advances in cell phone technology and networking have been pretty fascinating over the last decade or so. Have you studied that much yet? And the advances in fiber optic very high speed communication involve some very interesting physics and high-speed circuit design. And the emerging RF networking technologies (Bluetooth, WiFi, ISM sensing/control, etc.) have some very interesting components (mesh networking, etc.).
arvik
#3
Mar15-08, 01:18 AM
P: 6
hey thnx for replying.U see I havent done much of communication yet just started with modulation n things.Nevertheless I came up with atopic of my own.
U know there has been a lot of talk about chip industry reachin its limit.So I thought I would xplain the chip manufacturing process then xplain its limitation and talk about emerging technologies to replace itlike-quantum computin,molecular and bio(using neurons) computing.But I need a little help on the part where i xplain the limitation of the chip process and also if u could help me find some material on molecular and bio computing coz these topics r still in their infancy n I cant find much material to study about them

Ouabache
#4
Mar16-08, 02:28 PM
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P: 1,326
Paper presentation(Electronics and telecommunication engineering)

Let me also welcome you to PF !! As you will discover, by participating in these forums, you will find a wealth of information and guidance at your fingertips.

what do you think is limiting the integrated circuit process for future development?
For molecular & bio-computing, i would start with a web search. Any pertinent pages you find, I would follow up the references given on those pages. Also don't forget your university library, their reference librarians can assist in pointing out literature that pertains to your technical presentation.
arvik
#5
Mar17-08, 09:51 AM
P: 6
Quote Quote by Ouabache View Post
Let me also welcome you to PF !! As you will discover, by participating in these forums, you will find a wealth of information and guidance at your fingertips.

what do you think is limiting the integrated circuit process for future development?
For molecular & bio-computing, i would start with a web search. Any pertinent pages you find, I would follow up the references given on those pages. Also don't forget your university library, their reference librarians can assist in pointing out literature that pertains to your technical presentation.
Well I had read somewhere that intel is developin a process which uses "extreme ultraviolet light photolithography tool" which will help make chips with an average feature size of 32 nanometers.Now even the atoms of silicon and the doping material occupy some space so they can't just go on decreasing the size of components on ICs.I mean there must be some limit to it.
Secondly,I had also read that as we try to increase the packing density the doping material starts to clump together so even this would put a limit on the minimum size of the components on the IC.
I found only these two limitations coz of which sometime in the future the ICs will reach their max limit of development and then their will be stagnation.If u could point out something else which might be helpful then I would really be thankfulto u.And ya could u xplain which methods r used to prevent the clumping of the atoms of the doping material.
Ouabache
#6
Mar19-08, 02:19 AM
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P: 1,326
Well I had read somewhere that intel is developin a process which uses "extreme ultraviolet light photolithography tool" which will help make chips with an average feature size of 32 nanometers.Now even the atoms of silicon and the doping material occupy some space so they can't just go on decreasing the size of components on ICs.I mean there must be some limit to it.
So you've run across one of the limiting factors of constructing circuits on an IC, photolithography, where the wavelength of light used, poses a limitation. The shorter the wavelength, the smaller the architecture that may be drawn on the mask.
You may want to look up "Moore's Law" & see how this applies to your topic.

I can get you started with an article; but since this is your presentation, I'll let you find the rest. Pushing the limits of lithography for IC production. If you are an IEEE member you may be able to access on line otherwise take a look in your local college library.

Secondly, I had also read that as we try to increase the packing density the doping material starts to clump together so even this would put a limit on the minimum size of the components on the IC. I found only these two limitations coz of which sometime in the future the ICs will reach their max limit of development and then their will be stagnation.
So besides the imaging process, the IC construction (deposition & etching of material onto bulk silicon), also poses a limitation.

One general reference that I recommend is Semiconductor Manufacturing.
During construction, dust contaminants in the fabrication area, initially posed no major concern, but as the architechture began to shrink, these particles did interfere with IC function and reliability and ways to reduce contaminants needed to be addressed. I don't know about clumping of atoms of the dopant, however this sounds like a deposition issue.

Other areas that you may want to look into.. Here is an excerpt of an eetimes article that discusses some additional limitations Experts spar over limits of IC scaling.
Mark Bohr, an Intel senior fellow and director of process architecture...
"Besides scaling, there will be other major barriers going down the technology curve. ''Power density is the limiting factor,'' Bohr said. ''There will be less emphasis on frequency and a new emphasis on power efficiency.''

In addition, voltage barriers, velocity limitations and variability are becoming a concern going forward, said Hans Stork, senior vice president and chief technology officer at Texas Instruments Inc. ''The physics are working against us,'' Stork said. "
If u could point out something else which might be helpful then I would really be thankfulto u.And ya could u xplain which methods r used to prevent the clumping of the atoms of the doping material.
M.MANOJ
#7
Dec24-11, 07:41 AM
P: 1
I need some paper presentations on electronics engineering field
Rashmi Rao
#8
Feb18-12, 09:44 AM
P: 1
I need some paper presentation topics on electronics field


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