Memory Bus Addressing: Understanding Offsets in System Architectures

[TheAnalogKid83]

I've been looking at system architectures, and it seems almost always, a specific device on the memory bus uses a staggered type of addressing. What I mean by this is that say you have a chip select exclusive to 1 device. The address bus may have lines A[25:0], but instead of matching each address up (A0 of the memory controller to A0 of the device, A1 to A1, and so on), they are offset like maybe A10-A22 of the controller are attached to A0-A12 of the peripheral correspondingly.

I know each chip select has its own mapping, but why bother with the different addressing offsets? If its important, how do I know what I'm doing? There seems little reason that I can see from just looking at a schematic. I know some devices have page mode, where you're actually accessing a chunk of data, so maybe this is the only reason to have offsets? Along these lines, I've noticed almost always that the LSB of the controller address lines are the ones skipped.

Please, can someone with some experience with this give me an idea of what's going on here? Any tips for when I want to do this with different devices?

 

[anorlunda]

I'm not completely sure I understand your question. But I think the answer is to reduce the number of bits for addressing.

Consider a computer with 64 bit address range. How would it interface with memory devices having fewer than 64 bits address range? Clearly, you must partition the 64 bit range so that each device can take an address relative to the partition start.

 

[Rive]

I'm not sure if this is what you are asking about but something like this started with the 80386 CPU (among the PCs, I mean). Since the CPU had 32bit data bus the original byte-addressing became problematic, so the last two address lines were replaced by four byte-select lines.
Later on as the internal caches became common the actual addressing on the memory is no longer byte-address, but whole cache line address, since the whole data block were moved in bursts every time it got addressed: for example i7 has 64 byte cache line size which is always filled with one memory transaction, so the last six lines of a byte-address is omitted.
A further trick comes with the usage of dynamic memory addressing: as there is separate row and column address, the actual address line number is halved (with half the address provided only if the new request is off-page).