Optimizing Your 4 Layer PCB Stack-up for Maximum Performance: Tips and Tricks

[j777]

I'm designing my first SBC which will (hopefully) run Linux. The board will have the following:

Features:
AT91SAM9XE128 MCU at 180MHz (not in production yet but hopefully soon)
128MB SDRAM
128MB NAND Flash
16MB Serial DataFlash
10/100 Ethernet
33.6 Analog Modem (MultiTech SocketModem)
SD/MMC Slot
Battery Backed RTC

Power:
5VDC Input
1.8V MCU Core
3.3V Everything else

I'd like to design the board using 4 layers so I've been looking for a good 4 layer stack-up. The following stack-up has caught my attention (see figure 3b at http://www.hottconsultants.com/techtips/pcb-stack-up-2.html" ) :
1 - GND
2 - Sig/Pwr
3 - Sig/Pwr
4 - GND

While I'm not an EE expert there are a couple of things that seem to be real positive about this stack-up. For example:

• GND on the first layer provides a low inductance connection for decoupling capacitors and significantly reduces the number of vias.
• Layout is somewhat easier because no space taken up by vias for GND connections.
• Since I only have 2 supply voltages that have to be distributed around the baord and the 1.8V supply is only for MCU core it's easy to combine power with the signal layers.
• As noted on the above listed website this stack-up performs well from an EMC standpoint.

I have 3 questions regarding this stack-up:

1. What are additional pros/cons/gotchas for this stack-up that I should know about?
2. How should the two GND planes be connected? Only stitched together around the edges of the board or connected elsewhere as well?
3. Am I correct in thinking that I should try to keep signals on one of the signal layers rather than switching between layers to provide good return current paths?

Thanks

 

[berkeman]

Your PCB sounds complex enough that I'd initially shoot for a 6-layer board. If you can route it well on just 4-layers, including good grounding, then go for it.

The traditional stackup is Sig1-GND-Pwr-Sig2. Transmission line traces are run on the top layer only, to maintain a consistent Zo (feeding through to Sig2 adjacent to Pwr will spike the Zo -- bad). You can use some of the Pwr layer to route traces too, but generally will try to keep the GND layer as clean as possible. Also be careful about cutting up the GND layer with too many vias in a row -- that's a common cause of high-frequency problems.

You could put the GND and Pwr layers on the outside, but then you are cutting up the GND layer a lot for the SMT pads for the parts. You can use GND pours on the Sig1 layer and Sig2 layer after you are done routing, and stitch the pours to the inner GND layer.

Have you done a floorplan and rat's-nested it yet in your layout tool? That will start to show you about how many routing layers you are going to need. Remember to keep your decoupling caps on the same side as the IC they are decoupling, and keep all transmission line traces on a layer adjacent to GND, and don't feed them through the PCB.

 

[j777]

Ok...so if I understand what your saying properly I can do the following:

1. Sig1 - Most transmission lines (I definitely can't fit them all on this layer)
2. GND - Ground plane
3. Pwr - Power and the rest of the transmission lines that I can't fit on Sig1
4. Sig2 - Low frequency stuff

If the above routing strategy will perform well I may be able to get the job done with 4 layers.

On the other hand my life would be a lot easier with 6 layers. Google seems to tell me that with 6 layers I could do something like the following:

1. Sig1 - Mostly just SMT pads
2. GND - Ground Plane
3. Sig2 - Transmission lines
4. Sig3 - Transmission lines
5. Pwr - Power plane
6. Sig4 - Low frequency stuff

I've never used a 6 layer design before so this is uncharted territory for me. Is the stackup above the traditional 6 layer stackup or am I misinformed? Also, roughly how much more can I expect a 6 layer board to cost?

 

[berkeman]

The PCB cost ratios about with the number of layers, to a first order.

Your stackups look good. Keep in mind that the Zo is different for the different layer combos you show. The distance in the 4-layer PCB from Sig1 to GND is usually less than from GND to Pwr+Sigs. You will need to find out what the spacings are for any layer combos you want to use for TLs, and adjust your terminations accordingly.

 

[j777]

For the 4 layer stackup the spacings are Sig1->8.3mil->GND->39mil->Pwr/Sigs->8.3mil->Sig2.

For the 6 layer stackup the spacings are Sig1->8.3mil->GND->14mil->Sig2->8.3mil->Sig3->14mil->Pwr->8.3mil->Sig4.

This is the first design where I have to consider the Zo of the transmission lines (everything else I've done has been low frequency). After doing some reading it seems like the consensus is that if the lines are less than 1-2 inches in length termination is not necessary. Is this true?

In the 6 layer stackup is the Zo different for layers Sig2 and Sig3 even though they are the same distance from the closest plane? If yes, why?

 

[berkeman]

For the 4 layer stackup the spacings are Sig1->8.3mil->GND->39mil->Pwr/Sigs->8.3mil->Sig2.

For the 6 layer stackup the spacings are Sig1->8.3mil->GND->14mil->Sig2->8.3mil->Sig3->14mil->Pwr->8.3mil->Sig4.

This is the first design where I have to consider the Zo of the transmission lines (everything else I've done has been low frequency). After doing some reading it seems like the consensus is that if the lines are less than 1-2 inches in length termination is not necessary. Is this true?

It depends on the frequencies and the rise/fall times of the logic, but 1-2 inches is probably fine for the devices you listed. As part of your reading, look at the differences between "forward termination" and "back termination".

In the 6 layer stackup is the Zo different for layers Sig2 and Sig3 even though they are the same distance from the closest plane? If yes, why?

Sig1 and Sig2 are the layers where you can count on a clean Zo for TL routing (well, two slightly diffferent Zo's). Sig3 would be a poor choice for a TL -- you really want to be adjacent to GND, not Pwr to make a clean TL. Trying to rely on decoupling of Pwr and GND to set up a TL with respect to Pwr will generally not work, IMO.

 

[j777]

Thanks for the response berkeman.

I found the following in the forum about forward and back termination.

The best way to do it is to use 50 Ohm coax for the cable (BNC or SMA ends), a 50 Ohm line driver IC, and forward terminate at the receive end with a 50 Ohm (moderate power) resistor. The receiver will then only get a 0V to 2.5V signal, if the 50 Ohm source had an open-circuit output voltage of 5V, so you will need to do some level translation, or other handling of the signal if you want to get back to a 5V clock at the receive end. You don't need a capacitor in series with the 50 Ohm forward termination resistor, as long as you use a real 50 Ohm line driver at the TX end.

If you don't want to invest in the power of a real 50 Ohm line driver IC, then the next best way to do this is with a "back termination" resistor, placed in series with the output of the TX device. There is no forward termination used at the RX end, when you use the back termination technique. You choose the value of the back termination resistor to be the Zo of the cable (50 Ohms), minus the output impedance of the line driver IC. This is done so that there is a minimal re-reflection of the signal back off of the TX end. So, when the TX output transitions, that propagates down the 50 Ohm coax to the RX IC input, where a potitive reflection is generated (because the RX input Z is > 50 Ohms). That positive reflection propagates back up the coax, but is damped out by the series combination of the back termination resistance and the output Z of the driver IC (which total 50 Ohms).

Back terminations are more commonly used in lower-power circuits, because standard logic families do not have enough output power to support a full 50 Ohm (or even 100 Ohm) forward termination.

Please explain how this applies to my situation?

In the 4 layer stack-up should I be worried about putting transmission lines in layer 3 since it is 39mils from layer 2 (GND)? It isn't quite as bad if I go with the 6 layer stackup and route transmission lines on Sig1 and Sig2 because Sig2 is only 14mils from GND.

 

[berkeman]

I found the following in the forum about forward and back termination.


Please explain how this applies to my situation?

Hey, who wrote that? Well, on most digital designs in the frequency range you are addressing, you don't really want to burn the extra power of forward termination, especially on wide busses. So you keep all of the memory array lines as short as possible, and generally have good signal integrity without any termination. But there are generally some clock lines that need to run around a bit, and so you generally use back termination on those, placing the series resistor as close as possible to the TX gate pin. You need to keep that TL clean, especially if it's multi-drop (run it through all of the RX pins, and don't stub off traces to get to pins), so that the reflection from the far end gets damped out cleanly by the back termination in series with the TX output impedance, and you don't get signal ringing anywhere on the trace. As long as you don't have too many fast clock lines that need to route a few inches, you may be able to get away with not terminating anything but those clock lines.

In the 4 layer stack-up should I be worried about putting transmission lines in layer 3 since it is 39mils from layer 2 (GND)? It isn't quite as bad if I go with the 6 layer stackup and route transmission lines on Sig1 and Sig2 because Sig2 is only 14mils from GND.

I wouldn't put any critical TL signals in the Pwr/Sig layer in the 4-layer stackup unless you can't help it. And if you do put some there, they cannot be feeding through, back and forth between the outer and inner layer. They would have to via straight down from the driver output, and via straight back up at the input to the (single)receiving pin -- no multiple vias and multiple receiving pins for an inner TL trace.

I'd recommend doing the floorplan (placing the parts in the right places with the right orientations to keep the signal flows as tight and clean as possible), and identifying the fastest and most critical signals. Then you can start thinking about how to handle the layers and stackups.

BTW, a *great* book for learning about all of this is "High Speed Digital Design, A Handbook of Black Magic", by Howard Johnson and Martin Graham. Howie writes a column for EDN as well, so you could search their website for more tips about high speed layouts.

 

[berkeman]

BTW (you may have already done this), you can possibly find the PCB layout layers for a similar SBC eval board on the web someplace. Look for developer boards or eval boards for similar processors, and see if they show the PCB layout layers (or at least the floorplan) in their user documentation. That should start to give you some ideas, especially for how to handle the fast memory array components.

 

[j777]

Thanks for all the help. I'm going to take another look at my floorplan as you've suggested and see what I come up with.

I think the only clocks that I have running around are the serial clock (SD/MMC card and DataFlash) and the system clock for the SDRAM; I may have to consider termination for these.

 

[j777]

I'm trying to figure out what's the best way to orient the two SDRAM chips. If I use the 4 layer stackup I should be able to get most of the address lines on the top layer OR get most of the data lines on the top layer. Which is it better to have on the top?

Another key aspect of the decision making process that's causing me some trouble is how to route the lines to both sets of RX pins (one set per SDRAM chip - 2 chips total). The language in your posts seems to suggest that staying on the same layer and "stringing" the SMT pads together is the best way (ie route through the first set of RX pads and snake around to the next set of pads). Is this correct?

 

[berkeman]

I'm trying to figure out what's the best way to orient the two SDRAM chips. If I use the 4 layer stackup I should be able to get most of the address lines on the top layer OR get most of the data lines on the top layer. Which is it better to have on the top?

Another key aspect of the decision making process that's causing me some trouble is how to route the lines to both sets of RX pins (one set per SDRAM chip - 2 chips total). The language in your posts seems to suggest that staying on the same layer and "stringing" the SMT pads together is the best way (ie route through the first set of RX pads and snake around to the next set of pads). Is this correct?

I googled SDRAM PCB layout tips, and got some good hits. Try a couple of the hits on this list:

http://www.google.com/search?source...=1T4GGLL_enUS301US302&q=sdram+pcb+layout+tips

The hits at RAM manufacturer and uC manufacturer sites look to be helpful (like the Freescale and Micron and Cirrus hits).

 

[j777]

Well I have one thing left to route on the board; the 1.8V power plane. I went with the 6 layer stackup and I have all the TLs on Sig1 and Sig2. I was planning on putting the 1.8V power plane on Sig3 under the MCU but some of the TLs run under the MCU. My concern is that the TLs that run under the MCU wouldn't have a clean Zo because they are closer to Sig3 than GND (14mil vs 8.3mil). Is this a valid concern? If so would it be better to put the 1.8V power plane on Sig4?

 

[berkeman]

Well I have one thing left to route on the board; the 1.8V power plane. I went with the 6 layer stackup and I have all the TLs on Sig1 and Sig2. I was planning on putting the 1.8V power plane on Sig3 under the MCU but some of the TLs run under the MCU. My concern is that the TLs that run under the MCU wouldn't have a clean Zo because they are closer to Sig3 than GND (14mil vs 8.3mil). Is this a valid concern? If so would it be better to put the 1.8V power plane on Sig4?

I'm not tracking the details of the question very well, but basically your TL traces should have a consistent physical geometry around them. They should not have traces or other features on adjacent layers crossing them. They either need to be on the surface layer above a GND layer, or buried between planes (or at least with GND layer traces running with them above and below. Hope that makes sense.

You can google microstrip transmission line for more details -- you may have done that already.

 

[j777]

Let me rephrase and recap...

Here's my stackup

1. Sig1 - Mostly just SMT pads
2. GND - Ground Plane
3. Sig2 - Transmission lines
4. Sig3 - Transmission lines
5. Pwr - Power plane
6. Sig4 - Low frequency stuff

Here are the standard 6 layer spacings from the shop that makes the blank boards.

Sig1->8.3mil->GND->14mil->Sig2->8.3mil->Sig3->14mil->Pwr->8.3mil->Sig4.

I'm using a 3.3V supply for the MCU's IO and 1.8V supply for its core. I flooded layer 5 (PWR) with the 3.3V power plane because it is required all over the boad. The 1.8V supply only has to be routed to a couple pins on the MCU so my plan was to make a small power plane under the MCU on layer 4 (Sig3). The only thing that concerns me with this approach (1.8V plan under MCU on layer 4) is that it would be directly under some TLs on layer 3 (Sig2). Would the 1.8V plane routed on layer 4 disrupt the otherwise clean Zo that exists for the TLs on layer 3 because it would be closer to them than layer 2 (GND)?

Sorry for the confusion the first time around. Hopefully the question makes sense this time.

 

[sgaspar]

Hi j777,

It has been a year since your last post on this thread. I was wondering if you had success with this board.

 

[berkeman]

Hi j777,

It has been a year since your last post on this thread. I was wondering if you had success with this board.

He has not posted here in over a year. You can tell that by clicking on his user name and clicking on View Posts.

Still, he may get a notification e-mail about your post, and come back to update us.