Finding a min gate input count realization of enabling logic ?

In summary, the home security system has a master switch that can be used to enable an alarm, lights, video cameras, and a call to local police. If one or more of the six sensor sets detects an intrusion, then all of the outputs will be on.
  • #1
mr_coffee
1,629
1
Hello everyone, I'm confused on what they want me to do here:
it says:
Find a minimum gate input count realization of the enabling logic using AND and OR gates and inverters. Well This is my truth table i came up with, and the "enabler" is the M, the master switch( 0 secruit system on, 1 secuirty system off). Here is the picture: http://img145.imageshack.us/img145/6249/lastscan0oh.jpg any help would be great.
 
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  • #2
You do not fully state what your problem is. Can it be assumed that there are seven imput variable lines (the six "S" lines, and the enable M)? If so, then there are 2^7, or 128 possible input line combinations. That makes for a long truth table, but it isn't difficult to work with. There are two basic approaches to working with this. 1) Either you can put everything into a 128 combination truth table, or 2) for each desired output line, you can eliminate all inputs that don't pertain to it, and then make four truth tables, one for each of those desired outputs.

First, though you need to specify clearly what the inputs mean, and from this what input combination drives each of the outputs.

KM
 
  • #3
A home security system has a master switch that is used to enable an alarm,lights , video cameras and a call to local police in the event one or more of six sets of sensors detects an intrusion. the inputs, outputs and operation of the enabling logic are specified as follows:
inputs:
Si, i=0,1,2,3,4,5 - signals from six sensors sets(0-intrusion detected, 1 - no intrusion detected)
M-master switch(0 -security system on, 1-security system off)

outputs:
A-alarm (0-alarm on, 1 - alarm off)
L-lights(0-lights on ,1-lights off)
V-video cameras(0-video cameras off, 1-video cameras on)
C-call to police(0-call off,1-call on

Operation:

if one or more of the sets of sensros detects an intrusion and the security system is on , then all outputs are on. otherwise all outputs are off

find a minimum gate input count realization of the enabling logic using AND and OR gates and inverters.

------
PLZ HEEEEEEEEEEEEEEEEEEEEEEELP

it is so vital for me to find the solution urgently ,

any hints are welcome,,,,

TNXXXXXXXXX
 
  • #4
A home security system has a master switch that is used to enable an alarm,lights , video cameras and a call to local police in the event one or more of six sets of sensors detects an intrusion. the inputs, outputs and operation of the enabling logic are specified as follows:
inputs:
Si, i=0,1,2,3,4,5 - signals from six sensors sets(0-intrusion detected, 1 - no intrusion detected)
M-master switch(0 -security system on, 1-security system off)

outputs:
A-alarm (0-alarm on, 1 - alarm off)
L-lights(0-lights on ,1-lights off)
V-video cameras(0-video cameras off, 1-video cameras on)
C-call to police(0-call off,1-call on

Operation:

if one or more of the sets of sensros detects an intrusion and the security system is on , then all outputs are on. otherwise all outputs are off

find a minimum gate input count realization of the enabling logic using AND and OR gates and inverters.

------
PLZ HEEEEEEEEEEEEEEEEEEEEEEELP

it is so vital for me to find the solution urgently ,

any hints are welcome,,,,

TNXXXXXXXXX[/QUOTE]
 

What is the purpose of finding a minimum gate input count realization of enabling logic?

The purpose of finding a minimum gate input count realization of enabling logic is to optimize the design of a digital circuit by reducing the number of logic gates required to implement a given set of logic functions. This results in a more efficient and cost-effective circuit design.

What is the process for finding a minimum gate input count realization of enabling logic?

The process for finding a minimum gate input count realization of enabling logic involves analyzing the truth table of the logic functions and using Boolean algebra and Karnaugh maps to simplify the expressions. This helps to identify redundant or unnecessary logic gates, which can then be eliminated to reduce the total gate count.

What are the benefits of finding a minimum gate input count realization of enabling logic?

There are several benefits to finding a minimum gate input count realization of enabling logic, including reducing the cost and complexity of the circuit, improving its performance and reliability, and making it easier to troubleshoot and debug.

What factors should be considered when finding a minimum gate input count realization of enabling logic?

When finding a minimum gate input count realization of enabling logic, factors such as the speed and propagation delay of the logic gates, power consumption, and the availability of different types of gates should be considered. Additionally, the desired output and input requirements of the circuit must also be taken into account.

Can finding a minimum gate input count realization of enabling logic be applied to any digital circuit?

Yes, the process of finding a minimum gate input count realization of enabling logic can be applied to any digital circuit that uses combinational logic. However, the level of optimization that can be achieved may vary depending on the complexity of the circuit and the logic functions it performs.

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