## Can overdrive voltage never be less than zero?

I had a test recently and one of the problems was pretty basic. It gave you a table with the voltages at the gate, source, and drain of the device. Vt (Threshold voltage) was also provided, which was +1V. From there we were supposed to find Vgs, Vov(Overdrive voltage), Vds and the region of operation of the device. So for one part of the table I was provided with Vs (voltage at the source) is +1V, Vg (voltage at the gate) is +1V, and Vd (Voltage at the drain) is +2V. I know Vgs is Vg-Vs which in this case is 0V. And Vds is Vd-Vs which is +1V. However for Vov I got -1V which is solved by the equation (Vgs-Vt) so that would be 0-1=-1. This was wrong on my test. Does this mean the overdrive voltage can never be less than zero? Please help!

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 Vt is from gate voltage to source voltage. Vt=+1V means you need +1V at the gate RESPECTED to the source, NOT +1V respected to 0V. In FET, you need to have Vgs exceed the Vt before the FET turns on. In your case, you correctly established that your Vgs=0V.......Which is below the turn on threshold of Vt=1V. The transistor is not even turned on. That's all it means. Another way to look at it is: Vt is the spec from the data sheet that you need Vgs to exceed Vt before the transistor turns on. This mean (Vgs-Vt) has to be slightly greater than 0V before the transistor turns on.
 You are right in that Vov=Vgs-Vt In your case, Vov would be negative. What does that mean? Well, there are two cases to consider in general when Vov < 0 (although it is obvious that the transistor is NMOS since Vt > 0; unless, of course, it was given that |Vt|=1, then it is a PMOS and your answer would be wrong! Although the voltage levels at the gate and source doesn't make any resemblance with PMOS transistors bias conditions.): 1- If it was an NMOS (n-channel) FET, then it will be OFF. It is clear because a positive potential at the gate (more than the threshold voltage when source is grounded) electrode is necessary to establish the electric field that will collect electrons from the source & drain, push free holes away from the substrate; that is, making a channel for current flow. So without the sufficient positive bias voltage you will have two back-to-back diodes in series between drain and source. 2- If it was a PMOS (p-channel) FET, then it will be ON . It should be, since the condition Vov < 0 is necessary for this type of transistor; the physical reasoning is the total opposite of what is said above about NMOS. I hope that helps / One important note: What I said above, is not "entirely" true in that for values of Vgs less than but close to Vt, a small drain current flows. This is called Subthreshold operation. It has rare (but a growing number) of applications, and usually we ignore this region of operation, for simplicity.