Implementing Address Decoder for 68k: 4MB EEPROM, 1MB RAM, 4MB DRAM, 128B I/O

[EEstudentNAU]

I am asked to implment an address decoder for the 68k with the following units: 4MB of eeprom using 512k*8 chips, 1 MB of RAM using 128k*8 chips, 4MB of DRAM using 512k*4 chips, and 128 bytes of i/o space.

I do not understand the question very well, and any help would be appreciated.

 

[berkeman]

I'm not familiar with the Motorola 68k series, so I need to ask how many address and data lines does it provide? You need to draw out a memory map with the 24 memory chips mentioned in the question plus the memory-mapped IO. The EEPROM will most likely be at the bottom of the memory map (starting at 0x000000), since the 68k will need some non-volatile memory to run its boot program from, and I'd guess the 68k starts executing at 0x000000 after reset (is this right?).

So the 8 EEPROM chips take up the first 4MB of the memory map, from 0x0000 to 0x3FFFFF (divided into the 8 half-MB chunks), the 8 SRAM chips would go next, from 0x400000 to 0x4FFFFF, and so on. The last 128 bytes at the top after the DRAM chips are memory-mapped IO.

Now you need to look at the memory control lines for each type of memory, and design a circuit that takes in the address lines and the control lines from the 68k (like R/W- or whatever), and generates the enable lines for the different memory chips (like OE-, CS-, etc.). For example, when your decode circuit sees the address 0x000000 and the appropriate control lines from the 68k, it will generate a CS- for the bottom EEPROM chip (and *only* that chip), along with an OE- if it is a read cycle, or a WE- if it is a write cycle.

You typically would implement this kind of memory decode circuit in a CPLD or an FPGA. You can use Verilog or ABLE or whatever to code up the CPLD/FPGA. How are you asked to code up and simulate/test this design?

 

[piercas]

Sure, I can provide some guidance on how to implement an address decoder for the 68k with the given units. An address decoder is a critical component in any computer system as it is responsible for translating memory addresses into physical locations in the system's memory. Essentially, it takes the address provided by the processor and determines which memory unit should be accessed.

To implement an address decoder for the 68k with the given units, you will need to first understand the memory map of the 68k. The 68k has a 24-bit address bus, meaning it can address up to 16MB of memory. However, in this scenario, we are only dealing with 9MB of memory (4MB EEPROM + 1MB RAM + 4MB DRAM). This means that the remaining 7MB of address space is not being used.

The first step in implementing the address decoder is to determine the address ranges for each memory unit. For example, the 4MB EEPROM will use addresses 0x000000 to 0x3FFFFF, the 1MB RAM will use addresses 0x400000 to 0x4FFFFF, and the 4MB DRAM will use addresses 0x500000 to 0x8FFFFF. The 128 bytes of I/O space will use addresses 0x900000 to 0x90007F.

Next, you will need to select the appropriate memory chips to use for each unit. In this case, you will need to use 512k*8 chips for the EEPROM, 128k*8 chips for the RAM, and 512k*4 chips for the DRAM. These chips will need to be connected to the address bus and the data bus of the 68k.

Finally, you will need to design the logic circuit for the address decoder. This circuit will take the 24-bit address provided by the 68k and decode it to determine which memory unit should be accessed. This can be done using a combination of AND, OR, and NOT gates.

For example, to access the EEPROM, the address decoder circuit will check if the address falls within the range of 0x000000 to 0x3FFFFF and if so, it will enable the chip select signal for the EEPROM. Similarly, for the RAM, the circuit will check if the address falls within the range of 0x400000 to 0x4FFFF