Hazard-free AND-OR circuits proof

[Orikon]

I've been at this for a while now and I'm getting nowhere. The problem is to prove that a two level AND-OR (sum of products) circuit corresponding to the complete sum of a logic function is always hazard free (static hazard). I can't even figure out where to begin with this, any help would be appreciated

 

[berkeman]

What is meant by hazard free? I'm not familiar with that term in the context of logic design. Are you talking about metastability in flip-flop and latching circuits?

 

[piercas]

I can understand your frustration with this problem. Proving that a two level AND-OR circuit is always hazard-free is not an easy task. However, there are some steps you can take to approach this problem.

Firstly, it is important to understand what hazards are in the context of digital circuits. Hazards occur when there is a temporary incorrect output due to a delay in the propagation of signals through the circuit. In an AND-OR circuit, hazards can occur when there is a difference in the propagation delay of the inputs.

To prove that the circuit is hazard-free, you will need to show that all possible input combinations result in a stable output. This can be done by analyzing the circuit using Boolean algebra and truth tables. By simplifying the Boolean expression for the circuit, you can determine the necessary conditions for the output to be stable.

Another approach is to use Karnaugh maps to minimize the Boolean expression and identify any potential hazards. This method can help you visualize the circuit and identify any areas where hazards may occur.

Additionally, you can use timing diagrams to simulate the circuit and observe the output for different input combinations. This can help you identify any potential hazards and understand the behavior of the circuit.

In conclusion, proving that a two level AND-OR circuit is hazard-free requires a thorough understanding of Boolean algebra, truth tables, Karnaugh maps, and timing diagrams. It may also be helpful to seek assistance from colleagues or consult relevant literature on digital circuits. With careful analysis and experimentation, you can successfully prove that the circuit is indeed hazard-free.