Design a synchronous counter that has a Moore output decimal

[trickae]

Homework Statement

(Problem 205) Design a synchronous counter that has a Moore output decimal
sequence of 0, 1, 3, 5, 7, and then repeats this same sequence over and over. To
ensure illegal state recovery, force all unused or illegal states to go to 0. Carry out
the design using positive edge-triggered T flip-flops. Draw the circuit diagram.

Homework Equations

The Attempt at a Solution

I have no idea how to begin to attempt the solution any tips would be highly appreciated
currently reading wakerly chapter 7 to cover the basis of the problem

 

[berkeman]

What does a Moore machine look like. Show us your state transition diagram, and we can help if you still are confused.

 

[piercas]

I would approach this problem by first understanding the basics of synchronous counters and Moore outputs. A synchronous counter is a digital circuit that counts a sequence of binary numbers in a specific order, and a Moore output is a type of output that depends only on the current state of the counter, not the inputs.

To design a synchronous counter with a Moore output decimal sequence of 0, 1, 3, 5, 7, and then repeats, we can follow these steps:

1. Determine the number of states needed: Since the desired sequence has 5 decimal numbers, we will need at least 3 flip-flops to represent all the states (2^3 = 8).

2. Assign binary codes to the states: We can assign binary codes to each decimal number in the sequence as follows: 0 = 000, 1 = 001, 3 = 011, 5 = 101, 7 = 111. This will ensure that the counter goes through the desired sequence.

3. Determine the next state logic: Based on the desired sequence, we can write the next state logic table as:

Current State (Q2 Q1 Q0) | Next State (Q2' Q1' Q0')
000 | 001
001 | 011
011 | 101
101 | 111
111 | 000

4. Implement the next state logic using T flip-flops: We can use T flip-flops to implement the next state logic. The T flip-flop has two inputs: T (toggle) and CLK (clock). The output changes to the opposite of its current value (toggle) when the CLK input transitions from low to high (positive edge). We can use the T input to implement the desired sequence by connecting it to the appropriate states.

5. Draw the circuit diagram: The circuit diagram for a 3-bit synchronous counter with T flip-flops would look like this:

CLK ----| >|-----| T2 |-----| T1 |-----| T0 |-----
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