Understanding Phase Locked Loops (PLLs) with Phasors

[samski]

But as I said, the input to the PLL has to be frequency. that's how PLL work, you have a LO, you input a certain frequency $\omega$, the PLL will take the difference between the input frequency and the LO frequency and generate a voltage.

no it actually takes the difference in phase between the input and the output sinusoids. that's why there is a "phase detector". think about it, if what you said is right, then when the input frequency and the LO frequency are the same, there would be no voltage, so what is driving the VCO??

that is where $V_1 =K(\theta_0-\theta_{ref})$. Before it lock, the difference in phase between the two will create a voltage V1 that move the LO towards the in coming frequency. Then it become DC when the frequencies equal and lock. Under modulation, V1 will show the modulation. PLL is a down converter like IF stage of a AM or FM radio.

imagine you put an oscilloscope on the input to the PLL. you see a sinusoid yea? that's the x in my equation, x=sine(f(t)) is a sinusoid that is progressed according to a function of time.

 

[yungman]

no it actually takes the difference in phase between the input and the output sinusoids. that's why there is a "phase detector". think about it, if what you said is right, then when the input frequency and the LO frequency are the same, there would be no voltage, so what is driving the VCO??imagine you put an oscilloscope on the input to the PLL. you see a sinusoid yea? that's the x in my equation, x=sine(f(t)) is a sinusoid that is progressed according to a function of time.

x and y cannot be frequency as they only go from +1 to -1. They cannot be the frequency.

I miss spoke, the difference in frequency gave the difference in phase and the phase is changing. Read the pull in description of PLL and look at the graph of V1 as it pull in. During the pull in but before locking, V1 actually oscillating at the difference frequency with an offset in somewhat like a sine wave. But as the two frequency approached, V1 oscillate slower and slower until the two frequency equal and V1 become a DC. At this time, the loop is locked.

This is shown in p170 of the Phase-Look Basic by William F Egan.

 

[jim hardy]

i had to build a pll and study it with an osclloscope to grasp what goes on.

before lock the error voltage is bizarre looking AC

i too had to re-adjust my use of term "phase"

i was hung on question "how can you say there's a phase between sinewaves of two different frequencies?"
answer is it's a fleeting thing, and probably not mathematically pure at least at my level.

but seeing on the 'scope was believing. that old Signetics book does a petty good job.
years later i built a primitive PLL based telemetry system sending Touch-Tone signals via ultrasonic carriers around a plant's industrial PA system.
sure do wish National would bring back their TP5088 encoder.

 

[yungman]

phase difference of two sine wave of different frequency is nothing more than and continuous changing phase.....as their phase difference are changing from moment to moment and if the two frequencies are constant, your rate of phase change is constant also. Differentiating this phase will give you the difference frequency of the two.

I think you are a better person than me to continue the discussion as this get into closed loop Laplace transform quickly after the op clear up the confusion of phase vs frequency vs trig function of a phase ( sin x).