Are 3.3V Supply Glitches on CPLD Safe? Exploring Solutions for Reducing Noise

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In summary, using a CPLD as an IO expander, power supply glitches can be seen with a 7ns period. This can be corrected by using .01uF decoupling caps for the CPLD.
  • #1
j777
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Hi,

I'm using a CPLD as an IO expander and I'm seeing +/- 200mV glitches with a 7ns period on the 3.3V supply (the CPLD uses this supply) when output pins are switched on and off. Based on the CPLD's datasheet the acceptable voltage range is 3.0V-3.6V. Are these glitches typical/safe or should I add some low value caps to cancel some of this noise?
 
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  • #2
Power supply decoupling is key in fast circuits. I use one SMT 0.1uF decoupling cap for each Vdd input on an IC, placed on the top side of the PCB directly butted up next to the Vdd pin, with an immediate via to the Ground layer. If it's a 2-sided PCB, use ground pours on the top side to lower the Z and via to ground pours on the bottom side.

Also, when you are checking fast signals with an oscilliscope probe, it's important to use a Z-lead probe tip to lower the inductance of the ground return for the probe. If you don't have a standard Z-lead tip attachment, you can make your own with a small spring or even a paper clip.
 
  • #3
I have an SMT 0.1uF decoupling cap for each of the Vdd input pins as you have described. Is a supply glitch like this typical for digital outputs or should I begin to dig deeper?
 
  • #4
j777 said:
I have an SMT 0.1uF decoupling cap for each of the Vdd input pins as you have described. Is a supply glitch like this typical for digital outputs or should I begin to dig deeper?

It does sound a bit excessive to me, but I could be wrong. How many outputs are switching simultaneously to cause this glitch? Some FPGA/CPLD parts have limitations on how many outputs can switch simultaneously, if they are using a smaller package without lots of Vdd and ground pins. Maybe check your CPLD datasheet and app notes to see what they say about "simultaneous switching" of outputs to see if there are any limitations.
 
  • #5
I'll check the datasheet for simultaneous switching limitations but I'm only switching 8 simultaneously (for that 8-bit general purpose bus we were talking about in my last post).
 
  • #6
Interesting. Is there any chance that you have a timing violation when you are driving the bus, and are getting a temporary contention when you enable your output drivers? (Not likely -- I'm just throwing out ideas here.)

Are you using a Z-lead probe to check this glitch? It eliminates the ground wire of the probe, and instead provides a very short (<1cm) ground connection between the coaxial ground shield at the tip and a nearby ground point on your PCB.
 
  • #7
I am not using a Z-lead probe. How does this effect what I am seeing (I really don't know...I'm not trying to be smart)?

It is very possible that I have a timing violation when driving the bus...as you know this is my first go at this stuff. During a write (ie setting of outputs) the bus isn't driven by the CPLD though.
 
  • #8
Nevermind the z-lead probe question. I actually googled it and came up with a snippet from a pdf on your company's website. It sounds like this could be my problem (or lack of problem).
 
  • #9
Well I grounded my probe a little better and the glitch is at most +150mV/-110mV and I suspect I'd find that it's not even that much if I had a z-lead probe.
 
  • #10
I actually found some good information regarding supply decoupling for FPGAs and CPLDs on Altera's website that is helpful.

http://www.altera.com/support/devices/power/integrity/pow-integrity.html" [Broken]

Based on this it looks like I should be using .01uF decoupling caps for the CPLD instead of .1uF. I'm going to make this change and see if it helps.
 
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  • #11
Great work, Jason. That's how it works in the real world, BTW. I still like 0.1uF 0603 SMT decoupling caps, as long as the series L from the connection traces and vias is VERY low. But trying a mix of 0.1 and 0.01uF is a good avenue to pursue.
 

1. What are 3.3V supply glitches and how do they affect CPLDs?

3.3V supply glitches are temporary fluctuations in the voltage supply of a circuit, often caused by noise or interference. They can have significant impacts on CPLDs (Complex Programmable Logic Devices) as they can cause unexpected behavior or even damage to the device.

2. What are some common causes of 3.3V supply glitches?

Some common causes of 3.3V supply glitches include electromagnetic interference (EMI), power supply noise, ground bounce, and crosstalk between adjacent traces on a PCB. These glitches can also be caused by faulty components or improper PCB layout.

3. How can I prevent 3.3V supply glitches in my CPLD design?

To prevent 3.3V supply glitches in your CPLD design, it is important to carefully consider your power supply and PCB layout. Use decoupling capacitors to filter out noise, keep power and ground traces short and wide, and isolate sensitive traces from high-speed signals. It is also important to choose high-quality components and perform thorough testing during the design phase.

4. What are the potential consequences of 3.3V supply glitches in a CPLD?

The consequences of 3.3V supply glitches in a CPLD can range from minor performance issues to complete failure of the device. Glitches can cause timing errors, unexpected behavior, and even damage to the device. In some cases, the CPLD may need to be replaced if the glitch causes permanent damage.

5. How can I test for 3.3V supply glitches in my CPLD design?

The best way to test for 3.3V supply glitches in your CPLD design is to use a digital oscilloscope to monitor the voltage supply while the device is in operation. You can also use specialized tools such as a power integrity analyzer to detect and analyze any glitches in the power supply. Additionally, performing thorough testing during the design phase can help identify and prevent potential glitches before the device is implemented.

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