How to think about ground planes

[gnurf]

I recently had a discussion with a guy who believes that by putting a big slot in his PCB ground plane he will protect his analog domain from the noise originating in his digital domain. I don't agree with this view (hence the discussion), for various reasons, but to keep this post on point I want to focus on the guy's analogy---or way of thinking about the ground plane.

His reasoning went something like this: When a digital IC switches from one state to another, the device will produce a large di/dt that depletes the immediate area (and decoupling cap) around the IC for charges. This, in turn, disturbs neighboring charges ("pulling" them in / "pushing" them out, gah) and creates waves from the point in the ground plane and outward just like a stone dropped in a pond. Even with a decoupling cap, the current needed at the instance the IC changes states will be almost infinite so it will cause these "waves" in the ground plane during the first few nano-moments, etc..

I'm not even sure if that's an analogy or what it is. I tend to think in terms of currents and where/how they return to their source, so this picture of a "pond of charges" or what the hell it is, bothers me.

I tried to play the game of analogies and suggested it was more like removing a drop from the Atlantic, and that the pond analogy was more accurate if you added Hurricane Katrina to the picture. The discussion didn't go anywhere from there... (I'm just an engineer, not a particle physicist)

So, any thoughts on IC injecting and removing charges from the ground plane and creating ripples across the plane?

 

[DragonPetter]

Usually an analog ground is separated from a ground plane with a small trace. He has the right idea generally, because you have to be careful for ground loops where the current in ground will travel the shortest distance and create voltage drops along the ground (the copper has parasitic inductance and capacitance, so ground is more like an antenna/transmission line than a lumped circuit at high frequencies). But on the other hand I have been told as a general rule of thumb to make ground planes as big and filled as possible, which I try to do unless there is an application note asking to do a special ground isolation like in the case of a ethernet magnetics.

I thought of it this way, if the ground plane is acting like an antenna, cuts in the ground will reduce the wavelengths that can travel along the conductor. I don't know if that puts any thoughts in your head about it.

 

[skeptic2]

What kind of logic is he using, CMOS?
What is his clock frequency?
How wide is his Vcc trace?
Does he use decoupling capacitors?

The effect that you describe I don't think is caused by a large di/dt but by a large switching current. The datasheet should tell you what the switching current is and what the switching time is. That should give you an idea of the magnitude of the problem. (You can learn a lot from a datasheet.)

"Almost infinite" is interesting concept and brings to mind a Woody Allen quote, "Eternity is a long time, especially towards the end."

 

[gnurf]

He has the right idea generally [...]

Could you expand on the ways you think the charge-makes-ripples-in-the-ground-plane way of thinking works, and how it is useful. Think a lonely driver and a load fairly close together on a large PCB---the "pond"-model predicts that the pair of them would create noise for sensitive analog devices on the other side of the board. By what mechanism would a switching IC "pollute" the entire ground plane?

 

[gnurf]

What kind of logic is he using, CMOS?
What is his clock frequency?
How wide is his Vcc trace?
Does he use decoupling capacitors?

The effect that you describe I don't think is caused by a large di/dt but by a large switching current. The datasheet should tell you what the switching current is and what the switching time is. That should give you an idea of the magnitude of the problem.

Anything that switches current at a fairly high frequency. Yes, you can assume decoupling. But what I'm trying to establish is whether or not noise spreads in the ground plane as the rings from a stone in a pond.

I'm unable to see beyond the fact that the driver and its decoupling capacitor (which is the source here) and a load will form closed loops where the current will flow. Only if you stupidly put you sensitive analog device so that its return current passed through said loops, will the digital devices cause noise problems for the analog device. That's my take on it, anyway.

 

[DragonPetter]

What kind of logic is he using, CMOS?
What is his clock frequency?
How wide is his Vcc trace?
Does he use decoupling capacitors?

The effect that you describe I don't think is caused by a large di/dt but by a large switching current. The datasheet should tell you what the switching current is and what the switching time is. That should give you an idea of the magnitude of the problem. (You can learn a lot from a datasheet.)

"Almost infinite" is interesting concept and brings to mind a Woody Allen quote, "Eternity is a long time, especially towards the end."

Isn't a large switching current also a larger di/dt?

 

[skeptic2]

Anything that switches current at a fairly high frequency. Yes, you can assume decoupling. But what I'm trying to establish is whether or not noise spreads in the ground plane as the rings from a stone in a pond.

I've never measured it but as any good designer will tell you, you try to keep digital and analog circuits separate so I guess the answer is yes. However the noise on Vcc should be greater by the relative resistivity of the Vcc trace versus the ground plane. So normally I would expect the switching noise on Vcc to be orders of magnitude greater than the noise on the ground plane. Likewise the greater the di/dt of the switching current, the more effective decoupling caps should be.

I'm unable to see beyond the fact that the driver and its decoupling capacitor (which is the source here) and a load will form closed loops where the current will flow. Only if you stupidly put you sensitive analog device so that its return current passed through said loops, will the digital devices cause noise problems for the analog device. That's my take on it, anyway.

The usual way of dealing with that problem is to join the analog and digital ground planes a single point.

 

[yungman]

I designed a lot of mixed signal circuits that contain sensitive analog and high speed digital and I did signal integrity contracts before in helping pcb layout. I personally never cut grounds. I always use single ground plane and I never have problem.

BUT this is an interesting question. Remember if you look at any logics family other than ECL, they always have push pull output. During switching there is always a very short time that both the top and bottom transistor turn on at the same time and large current drawn for that split second ( say nS or even pS). This is particular bad in CMOS logics where the turn-on threshold is unpredictable. You can find this in data sheet on Vcc current vs switching frequency. You'll see at some frequency, CMOS logic over take TTL at high switching frequency even though at static, CMOS do not draw nearly as much as TTL.

Noise generated everytime you switch output state regardless whether you sent the signal out to another part of the board or not. The di/dt is just as great regardless you switch in high frequency or one switch. This signal travel from the positive Vcc pin back to the Ground pin of the same IC. Theoretically if you have perfect bypass path, the noise will just travel from the Vcc to GND pin of the IC and going nowhere else. But we are talking about frequency components that reach into microwave frequencies and bypass cap really don't work so well. So noise do come out.

Back to your friend's assertion. Let's consider you do have a power and ground plane that connect to the IC's Vcc and GND pins resp. The noise will not come out like a stone drop in the pond and spread out to all direction. This is all governed by EM theory and transmission line theory. Whenever a signal come out that, there is always a source and a return, there is NO EXCEPTION on this. In this case, the source of the Vcc of the IC is the input power of the board, the return is the return of the power supply that power the board. Basically any noise that is not bypassed by the bypass cap is going to travel back to the power source input of the pcb. The question is what path the noise takes to the power source. EM theory govern that it will take the shortest distance from the IC to the power source AND the path is governed by the loop that encircle the minimum area. This mean that the forward and the return signal are right on top of each other. It behave exactly like stripline even though it really is a power and ground plane. Bottom line, the noise signal and return will find the shortest path from the IC to the power input of the pcb AND the source and return signal are traveling on top of each other like a stripline. Here are the reasons:

1) The reason of finding the shortest path is very simple. Copper do have resistance. Current density is highest at the path of lowest resistance and so it would be the shortest and most direct path! It is not going to go all directions and then go to the power input point to the pcb.

2) The reason why the signal and the return path always follow closely with each other unless there is an interruption is because the voltage/current signals travel as EM wave, not really as current or voltage like people want to think ( this is more complicated and not needed here). The current and voltage is only the consequence of the boundary condition of the EM wave traveling down the path as surface current density given by the EM boundary condition. EM wave do travel in a single path, so the induced current on both the power plane and ground do follow the path of the EM wave and keep closed to each other whenever possible. That is if there is no interruption.

In simpler term: In signal integrity engineer term, the signal path choose the path of LEAST INDUCTANCE. Which means the path that enclose the minimal area...Which imply they travel close the each other...one on top of each other.That said. To me, the best way is to design the pcb stack up that the power and ground planes are on top of each other and separate by 5mils of FR4 only. This will produce larger distributed capacitance between the two planes and this having large surface area, will produce almost an ideal cap ( at least in GHz range) that able to give a good bypass path between the Vcc and GND pin of the IC. Noise from Vcc to GND pin will almost go straight between the pins and not out. If you don't have a good coupling or power is not on a plane but only a trace, then you better worry more as signal not only on the ground but also the power trace.

Now come to the point of separate analog and digital ground. To me, this is more dangerous than you think. Read the 2) point that I gave again, if you make a cut in the wrong place that cause a disruption of the EM wave, the forward and return path of any signal trace will be forced to run a separate paths and increase the area enclosed and so forming a loop. AND you know how good a loop antenna in radiating EM wave! The EM theory described in 2) apply to signal output that drive to other parts of the board. The forward and return path always stay close unless that is a break and that's where the problem starts.

Think of if you have cut grounds, and the digital run on top from one ground plane to the other, return signal is disrupted and has to find a different path to complete the loop. You'll have interference all over. Hope this give you a better idea.

So in summary, signal DO NOT propagate out like stone drop in a pond. Separate ground plane is only good if you know exactly how the signal travel...Believe me, people think they know a lot more than they really do! But short of that, use single ground plane, make the power and ground plane close to each other to form an ideal cap to take care of the bypass when the 0.01uF cap starting to fade out.

With good layout technique, interference is not a problem. If you look at the current distribution on the ground plane under a microstrip ( exactly the same as signal trace running on the surface of a pcb with ground plane under), 90% of the current is contained within 4 trace width on each side of the trace with normal stackup. Meaning if your sensitive trace is greater than 6 to 7 trace width apart, you are pretty safe. There are so many mis-conception about grounding it's not even funny. Then the matter got worst when those professors that don't have a day in real life design is teaching electronics. Look at all the books, they concentrate on all the fancy theories and they treat power and ground as just a connection! Power and ground are the most difficult part of the design. If you take care of this, circuits actually work as describe in the books! All the problems mostly stamped from implementation of the circuit in real life...power and ground is not just a point...they are actually part of the circuit and that usually the part people get screwed...pardon my words.

 

[yungman]

I want to add, I design a 24" flex circuit ( flexible pcb) of about half inch wide. Inside, I have two 50Ω RF lines, a pair of 90Ω USB and two pairs of 110Ω Firewire( each FW is two pairs of differential lines). I designed the layout and stackup and I get over -25dB cross talk isolation between all different signals testing at 1.8GHz, that is very good. I designed so the dielectric thickness of the strip line is as thin as possible to accommodate a 4mil trace for the Firewire lines. That was the gating factor as 110Ω differential impedance require very thin trace and I don't want to use 3mil as the conductance loss start to build up and the eye start to close at the receiving end.

If I were to change the spec of the Firewire to 100Ω, I should be able to get even better result. There goes to show how close you can put digital signal and analog trace together. This is 24" running side by side! I won't be insisting on cutting ground because you stand to screw up much more than it will help.

 

[yungman]

I was really thinking about this over night as EM fascinate me. Please join in for discussion as this is really my opinion and I am not sure this is correct.

Let's say you are using a 4 layer board and traces are on the top and bottom layer only. power and ground as internal plane close to each other like what I said about only 5mils apart. My assertion is the trace on the top and bottom will not see any spike from the di/dt as mentioned in this post. This is my reasoning:

As I said before, it is the EM wave that propagates, EM wave in this case only confined in between the power and ground plane that form a GUIDED structure( think parallel plate transmission line). There is NO SURFACE CURRENT DENSITY on the top side ( or bottom side) of either plane. This is because you cannot have a guided structure on the top or bottom of the pcb to sustain the EM wave caused by the di/dt.

You might argue that current can conduct from bottom of the copper plane to the top, but that would not happen. The reason is at this frequency, current is absolutely confined as surface current. There is no penetration into the copper. If you want any surface on the top side and bottom side of the planes of the pcb, you are going to have to have EM wave propagation. This will not happen as there is no structure to promote an EM wave of the di/dt on the top and bottom side.

That said, my conclusion is the trace on the top and bottom layer should not see the di/dt effect. I am going to see whether I have PM some high power physics people like Cabraham and StevenB in the Classical Physics to comment on all my assertion, hope they are still hanging around here and can join in.

 

[gnurf]

Hey Yungman, thanks for sharing your experience. I agree with most of what you say, and find nothing in this thread to support the "pond-theory".

But, playing the devils advocate for a second I'd like to argue that in a high frequency and/or low decoupling capacitance (be it a discrete device or parasitic trace capacitance) scenario, the switching noise current loop formed by the totem-pole pair and back through the surrounding capacitance will expand in area. I'm picturing the di/dt spikes finding an increasing number of small parasitic caps around the driver, which would mean that a larger copper area (with a finite inductance) would see the di/dt and cause a noise voltage. If you measured the ground voltage at various points referenced to some other stiffer ground, it could appear as if the noise spread as the "pond-theory" predicts. Does this make sense?

(All of this could of course be remedied by proper decoupling and stackup, so it's still not an argument against a solid gnd plane.)

 

[Studiot]

Section 7.10, page 173 to 174 of the IEEE publication

Printed Circuit Design Techniques for EMC compliance, by Mark Montrose

is entitled

Ground Slots in Backplanes.

It discusses this matter and explains why return RF currents have to travel 'the long way round' slots and offers formulae.

See also page 36 of this publication.

 

[yungman]

Can you expand more as I don't belong to IEEE. What is the "long way around".

 

[yungman]

Hey Yungman, thanks for sharing your experience. I agree with most of what you say, and find nothing in this thread to support the "pond-theory".

But, playing the devils advocate for a second I'd like to argue that in a high frequency and/or low decoupling capacitance (be it a discrete device or parasitic trace capacitance) scenario, the switching noise current loop formed by the totem-pole pair and back through the surrounding capacitance will expand in area. I'm picturing the di/dt spikes finding an increasing number of small parasitic caps around the driver, which would mean that a larger copper area (with a finite inductance) would see the di/dt and cause a noise voltage. If you measured the ground voltage at various points referenced to some other stiffer ground, it could appear as if the noise spread as the "pond-theory" predicts. Does this make sense?

(All of this could of course be remedied by proper decoupling and stackup, so it's still not an argument against a solid gnd plane.)

You are talking about a different scenario already. If you have very good bypass around and you have bad bypass on one particular IC, then yes, it will seek the path of least resistance and in that case, will be from the surrounding bypass cap. I am talking about the ideal case where you have one IC with tolem poll and one source point. It's about the path of least resistance.

Even in my original reply, if you are looking at the moment the noise come out, it is spreading in all direction, but quickly turn toward the direction of least resistance. Think about the electric field of a simple dipole, at the moment the field leaving the +ve charge, the field lines are radiate in ALL directions evenly, but when they travel out, it start bending towards the -ve charge.

Also you have to consider the attenuation of the noise pulse. Theoretically, you never get zero, just how low it is when get the the sensitive analog trace. Of cause given in the perfect world, you will bet better isolation with separate grounds, but you really have to know what you are doing and account with every single signal trace to ensure you get the image current right. One mistake will cause you more problem than the little interference from the residue noise of a single ground plane.

 

[Studiot]

You don't need to be a member to obtain the book, which has lots of good recent advice/information for pcb designers.

 

[yungman]

I have the EMC and printed Circuit Board by Mark Montrose, not the one you mentioned, I prefer using the Howard Johnson and Martin Graham. I know you never like to give your opinion, but can you summerize what the book said so to save us time to read through the whole chapter? If you know what it's about, please tell us.

I don't know about slotted lines and the materials that I study all prefer single ground planes as I explained. We had a class with a very well known EMC person called Chris Kendell and he talked a lot about grounding. . He was a very sorted after person by companies to work on EMC in the industries as I worked for two different companies that used him as consultant. I interpretate all the ideas with EM theory.

 

[Mike_In_Plano]

I've spent the better part of my life working in precision analog.

The scope tells all. If you allow fast rise-time signals to route over your analog ground plane or to carry logic currents through your analog ground plane, you will have fuzzy signals, noisy A/D channels, and sometimes DC offset in your paths. Then, you'll wonder why your waveforms never look as pretty as those supplied in the data sheets.

 

[yungman]

I've spent the better part of my life working in precision analog.

The scope tells all. If you allow fast rise-time signals to route over your analog ground plane or to carry logic currents through your analog ground plane, you will have fuzzy signals, noisy A/D channels, and sometimes DC offset in your paths. Then, you'll wonder why your waveforms never look as pretty as those supplied in the data sheets.

If you talk about you have separate ground plane and you have digital signal run over the analog ground plane, yes then you have big problem as I explained before. This is the reason I recommended not to separate ground unless you know exactly what you are doing. It is easy to talk in the book about how to route the trace and keep away from the analog ground. In real life, it is not as easy, you make one mistake and there you go.

As I said before, if you have one solid ground plane and make sure you don't have separate power plane right under the traces, you are safer. Image current follow the signal trace and don't spread out.

 

[Dmytry]

I recently had a discussion with a guy who believes that by putting a big slot in his PCB ground plane he will protect his analog domain from the noise originating in his digital domain. I don't agree with this view (hence the discussion), for various reasons, but to keep this post on point I want to focus on the guy's analogy---or way of thinking about the ground plane.

His reasoning went something like this: When a digital IC switches from one state to another, the device will produce a large di/dt that depletes the immediate area (and decoupling cap) around the IC for charges. This, in turn, disturbs neighboring charges ("pulling" them in / "pushing" them out, gah) and creates waves from the point in the ground plane and outward just like a stone dropped in a pond. Even with a decoupling cap, the current needed at the instance the IC changes states will be almost infinite so it will cause these "waves" in the ground plane during the first few nano-moments, etc..

I'm not even sure if that's an analogy or what it is. I tend to think in terms of currents and where/how they return to their source, so this picture of a "pond of charges" or what the hell it is, bothers me.

I tried to play the game of analogies and suggested it was more like removing a drop from the Atlantic, and that the pond analogy was more accurate if you added Hurricane Katrina to the picture. The discussion didn't go anywhere from there... (I'm just an engineer, not a particle physicist)

So, any thoughts on IC injecting and removing charges from the ground plane and creating ripples across the plane?

Well, that would depend to how the current (that is being injected) is supplied. In general, yes, you can have ripples in the ground and power planes, yes they travel like waves in the pond, and yes, they can get into the analog side, and yes you are better off separating the analog power and analog ground from digital power and digital ground with a thin perhaps coiling trace (that would have inductance) or best yet a small inductor, and attaching a capacitor on the analog side. At high frequency you really do have ripples propagating. The power being your vcc.

edit: albeit the ripple is matched to a ripple in the vcc. When the IC suddenly starts consuming more power, the ripple of lower + voltage at + line and higher - voltage at - line starts off at the IC, goes towards source, reflects there as a ripple of higher voltage (or the voltage equal to vcc), and gets back to the IC. It also reflects off all the capacitors. If you have the capacitor in parallel to the IC between IC and rest of the circuit, it'll pretty much prevent the ripple from going anywhere past that capacitor (or at least decrease the ripple quite a lot). The computer boards are packed full of tiny capacitors for this (well, and some other) reasons. And indeed the image current ripple in ground won't spread out much from the line that is powering the IC.

Some devices, such as nitrogen lasers, even depend directly on the ripple propagation to set up the moving discharge in the channel.

 

[yungman]

Well, that would depend to how the current (that is being injected) is supplied. In general, yes, you can have ripples in the ground and power planes, yes they travel like waves in the pond, and yes, they can get into the analog side, and yes you are better off separating the analog power and analog ground from digital power and digital ground with a thin perhaps coiling trace (that would have inductance) or best yet a small inductor, and attaching a capacitor on the analog side. At high frequency you really do have ripples propagating. The power being your vcc.

edit: albeit the ripple is matched to a ripple in the vcc. When the IC suddenly starts consuming more power, the ripple of lower + voltage at + line and higher - voltage at - line starts off at the IC, goes towards source, reflects there as a ripple of higher voltage (or the voltage equal to vcc), and gets back to the IC. It also reflects off all the capacitors. If you have the capacitor in parallel to the IC between IC and rest of the circuit, it'll pretty much prevent the ripple from going anywhere past that capacitor (or at least decrease the ripple quite a lot). The computer boards are packed full of tiny capacitors for this (well, and some other) reasons. And indeed the image current ripple in ground won't spread out much from the line that is powering the IC.

Some devices, such as nitrogen lasers, even depend directly on the ripple propagation to set up the moving discharge in the channel.

Can you explain in theory about the ground plane ripple like stone drop in a pond that spread to all sides?

We assume there is bypass cap as in #5, we are talking about higher frequencies that the small 0.01uF bypass cap cannot even cover.

 

[es1]

His reasoning went something like this: When a digital IC switches from one state to another, the device will produce a large di/dt that depletes the immediate area (and decoupling cap) around the IC for charges. This, in turn, disturbs neighboring charges ("pulling" them in / "pushing" them out, gah) and creates waves from the point in the ground plane and outward just like a stone dropped in a pond. Even with a decoupling cap, the current needed at the instance the IC changes states will be almost infinite so it will cause these "waves" in the ground plane during the first few nano-moments, etc..

The common name for this is ground bounce. The reason charge depletes, producing a noticeable voltage drop, is due to the inductance of the power planes. (If there was no L there then nothing would resist the change in current and the local capacitance would fill immediately due to the voltage differential rebalancing charge before it got large.)

The classic app note on this is here:
http://www.fairchildsemi.com/an/AN/AN-640.pdf

There is basically two ways for this to be serious. Flip lots of small transistors all at once, or flip one really big one moving a lot of current. This is why you often see mentioning of ground plane routing in switching power supplies. But it is the exact same phenomenon as the digital one mentioned. See page 18 in this TI data sheet for an example:

http://www.ti.com/lit/ds/slus947a/slus947a.pdf

Here TI recommends splitting the ground planes (actually its more like making ground wells) as to not have the large NFET switching disturb the sensitive analog voltage feedback and trip set point measurement.

This is a tricky issue because a bad layout can make a circuit which should be perfectly ok fail. And because distinguishing between a good layout and a bad one analyitically is a lot of work there are a lot of rules of thumb out there, and they kind of morph into voodoo over time.

The app note is a good place to start. You might all look into how to design a power distribution network for a pure digital system. All the physics is the same as an analog system. Just the voltage ranges and frequencies differ.

In general personally I think this issue is usually overblown and one way I found out to tell how serious the issue really is is to ask for the noise budget of the net. If you don't see the person making a noise budget then maybe this signal is not as sensitive as they are pretending because if they really cared, they would need one. (Be careful on calling them on it though. I usually don't. :)

 

[es1]

But what I'm trying to establish is whether or not noise spreads in the ground plane as the rings from a stone in a pond.

This was already answered so I didn't address this but how about this thought experiment. Kind of basic but I think it works.

The geometry of a ripple, like a stone in a pond but in the ground plane, is inconsistent with the rule where ground current takes the shortest path back to the source as it would have to do a turn in a medium with uniform impedance (keep in mind the shortest distance between two points is a straight line). As voltage can only change where current flows, voltage noise does not radiate like a stone in a pond in a PCB ground plane.

 

[yungman]

I thumb through the first few pages of the first article. That is for IC internal device ground, nothing to do with the discussion here. You can actually see the IC device ground bounce by looking at one of the output when the other outputs are switching. You can sometimes see the "Low" have baby steps correspond to the switching of the other buffers in the same IC. Old DIP pack TTL or ACT had a lot of these problem because the Vcc and Gnd are at the extreme end of the package. The two connections are with a long small wire and the inductance are very high that cause the problem. The newer family have supply pins in the middle of the package that solve a lot of the problem. In doubt, choose the ones with ground and power leads in the middle of the package. Also surface mount components have much less of this problem because of the same reason even the pinout are the same as the wire is a lot shorter. Look at the newer LSI digital chips, they have many ground and Vcc pins for this reason. Make sure you put bypass on every single pin.

I agree with page 18 of the second article of the 3 loops. But I still say unless you know what you are doing, cutting ground is a dangerous matter. You have to take into account of every single trace to make sure each has the image path that don't have disruption. If you don't want to go through the pain, stay with one ground. I personally never use separate ground. We had use a lot of the small switching supply chips on small circuit boards and never have to worry about noise. The only time I had a project of a gun sight camera dump on me that had interference lines on the screen turn out to be two of those switching supplies instability and burst into oscillation. But that has nothing to do with grounding, just good old closed loop control system.

Layout is very important, you have to be very careful. Get the two books that I mentioned in the post on this thread. It is all about image current. People are too quick to blame everything on ground bounce. Not only look at the layout, look at the gerber plot of the ground plane. Those extra large size thermo relief can rig havoc on the ground when you think you get good ground connection but instead the ground all got cut up by the thermos. It is not simple, more engineer think layout is just layout, I can tell you layout is haft the design. I layout my own boards. PCB designers don't know anything about layout, they know the layout tool just like you know how to use Word program don't automatically make you writing good English. PCB layout is the real life art school don't teach you. I question how many of those professors know the meaning of layout.

But still all these are not really relate to the very original question. That the ground ripple on the pcb ground plane ripple like a stone drop in the pond and propagate out. I disagree with that. I still you have to use EM analysis for this one.

 

[es1]

I thumb through the first few pages of the first article. That is for IC internal device ground, nothing to do with the discussion here.

I think if you replace the instances of "pin" inductance with "path" inductance then all the equivalent circuit models stay correct and all the analysis holds. All the recommendations also hold true too: watch for the shortest path, beware overlapping current paths, etc.

In general their L1 and L2 is a lumped inductance anyway on PCBs as it includes the bypass effective ESL, the path inductance and pin inductances.

 

[es1]

But still all these are not really relate to the very original question. That the ground ripple on the pcb ground plane ripple like a stone drop in the pond and propagate out. I disagree with that. I still you have to use EM analysis for this one.

What did you think of the argument in #22?

I was thinking specifically of this case. Part of the current loop is a vector directly from point A to point B in the ground plane. In order to for a ripple around A to occur, there must be one ray that is in the exact opposite direction of this vector. But how does this current turn around to get back to B in a uniform impedance, which is what a ground plane is supposed to be.

 

[Antiphon]

The ripple is a valid model. Yungman refers to the idea that current flows in loops. This latter view is true at longer time scales. The ripple reaches the cap at the power supply and there is a reflected wave through the low impedance of the cap. This is Yungman's current loop beginning to form.

For very high frequency work the ripple concept applies. If the rise time of the pulse is much longer than the physical extent of the board vis-a-vis the speed of light, then you won't be able to resolve the pond ripples; you'll simply see the closed current loops Yungman described.

 

[Dmytry]

Can you explain in theory about the ground plane ripple like stone drop in a pond that spread to all sides?

We assume there is bypass cap as in #5, we are talking about higher frequencies that the small 0.01uF bypass cap cannot even cover.

Well the small cap should be covering the highest frequencies best unless it is too far or otherwise has too much inductance.

Basically, suppose you got two planes, like, a planar capacitor. One is ground plane other is vcc plane. Charged to some voltage. If you short the ground plane and vcc plane in one point you will get expanding circle of low voltage from that point. It is electromagnetic wave and it will (AFAIK) travel at the speed of light in the dielectric material (so we are speaking very high frequencies here, very rapid pulse risetimes. 1 light-nanosecond is 30 centimetres). It will also reflect off all the edges, and off capacitors you can have connected. It is fairly straightforward to simulate on computer. The equation for conductive plane is not too complicated, you just do the electromagnetic field between the plates and current in the plates. You do end up with equation much similar to elastic plane that can have free ends or be attached in some points. Not quite like a pond but kind of similar.

I'm not sure how much ripple can a chip generate. You'll have capacitors across any high speed chip like that, and probably it's own dedicated dc-dc converter as well.

When you don't have vcc plane but vcc wires, the behaviour gets more complicated but it will still generate electromagnetic waves through the ground plane outside the overlap area, I believe. It is hard to visualize in that case, I'd rather research literature on that. In principle one could solve this for a strip over a plane.

 

[yungman]

What did you think of the argument in #22?

I was thinking specifically of this case. Part of the current loop is a vector directly from point A to point B in the ground plane. In order to for a ripple around A to occur, there must be one ray that is in the exact opposite direction of this vector. But how does this current turn around to get back to B in a uniform impedance, which is what a ground plane is supposed to be.

I think there is two different scenarios that one has to distinguish. I am very sure about scenario (a). But I am just guessing about scenario (b).

a) Only ground plane and power trace: In this case, the ground current ABSOLUTELY follow the trace of the power trace. This is exactly like a microstrip where the image current follow the trace current. This is because it's the EM wave that travel and the surface current is only the consequence of the boundary condition. If you look at any of the EMC books, you will find that. There is no if and buts about it.

b) If you have both a power and ground plane next to each other and form a big capacitor, then the theory get complicated as which path the current take. There is still two cases:

Case b1 where there is no bypass cap around between the two planes and your di/dt happen at point A and the power source and sink at point B. My guess is described in post #14 where the EM field is a vector field look like the field lines of an electric dipole where it actually starts out radiating in ALL direction like ripple in a pond...BUT it quickly start changing direction because of the path of least resistance.

Case b2 where there are good bypass caps throughout the board. In this case, my guess is still the current take on the path of least resistance. But in this case the path might be where the closest bypass caps are, so the current density might be "stared" out reaching towards the few closest bypass cap.

 

[yungman]

Well the small cap should be covering the highest frequencies best unless it is too far or otherwise has too much inductance.

Basically, suppose you got two planes, like, a planar capacitor. One is ground plane other is vcc plane. Charged to some voltage. If you short the ground plane and vcc plane in one point you will get expanding circle of low voltage from that point. It is electromagnetic wave and it will (AFAIK) travel at the speed of light in the dielectric material (so we are speaking very high frequencies here, very rapid pulse risetimes. 1 light-nanosecond is 30 centimetres). It will also reflect off all the edges, and off capacitors you can have connected. It is fairly straightforward to simulate on computer. The equation for conductive plane is not too complicated, you just do the electromagnetic field between the plates and current in the plates. You do end up with equation much similar to elastic plane that can have free ends or be attached in some points. Not quite like a pond but kind of similar.

I'm not sure how much ripple can a chip generate. You'll have capacitors across any high speed chip like that, and probably it's own dedicated dc-dc converter as well.

When you don't have vcc plane but vcc wires, the behaviour gets more complicated but it will still generate electromagnetic waves through the ground plane outside the overlap area, I believe. It is hard to visualize in that case, I'd rather research literature on that. In principle one could solve this for a strip over a plane.

Actually if Vcc is a wire, it is a lot simpler as I explained using microstrip image current in post #28. The ground current just follow under the Vcc trace. There will be no stone in the pond. This is the whole base of EMC.

Regarding to case that have Vcc and Ground plane, remember the total energy of a di/dt pulse is constant, as the EM vector field radiate out, the magnitude decrease with distance, it is not like a pond even in your scenario of capacitor without any other source and sink point. With any bypass cap, my guess is the current density will follow the path of the least resistance which is the shortest point to the bypass cap, so it is again not like a pond.

 

[yungman]

The ripple is a valid model. Yungman refers to the idea that current flows in loops. This latter view is true at longer time scales. The ripple reaches the cap at the power supply and there is a reflected wave through the low impedance of the cap. This is Yungman's current loop beginning to form.

For very high frequency work the ripple concept applies. If the rise time of the pulse is much longer than the physical extent of the board vis-a-vis the speed of light, then you won't be able to resolve the pond ripples; you'll simply see the closed current loops Yungman described.

I have been thinking about your comment about the difference between a steady state ( long time scale as you said) vs a one shot reaction. I start to question this. Yes, I am looking at the point of view of RF or EM more in a continuous event where the di/dt occurred continuously as is most of the case in real life. It is like a series of pulses, not necessary at regular interval but is a continuous event. But you got me thinking about what if there is only one disturbance.

I believe if the Vcc is a trace and only ground plane exist, my theory of microstrip and image current still exist as this is still the only guide structure for EM wave to propagate.

BUT if you consider a full power and ground plane like a parallel plate capacitor, I start to question the one shot effect. I don't even know how to simulate this. Can you give us some reference on your assertion? This is getting very interesting.

 

[cmb]

I would also regard the 'pond ripple' analogy to be reasonable, but also that it is incomplete. When a switch opens up, it is allowing electrons to flow. That flow is motivated by a difference of potential between one location and another. The question, then, is whether the current is motivated by a potential some distance away, or a potential right next to that space. Logically it is the latter. Electrons will move locally, then further electrons will flow into the space they've left behind. They don't all flow like soldiers on parade, all at once to the sound of someone shouting an order, they flow like cars pulling off from traffic lights with each responding to the one next to it.

This is why you get overshoot, similarly. The electrons are all racing forwards and the switch is thrown open and they all crash into the back of each other like tailgaters on the motorway. They're real dumb, those electrons! Not a single brain cell between them!

OK, so what bit is incomplete? Well, this all happens on a timescale so short, relative to a PCB, that you're talking nanoseconds and miniscule levels of charge. If this was the only effect, it'd not be very significant.

But the thread so far has generally missed a discussion on the impedance of the circuit back to the sink/source. This is what will dominate the behaviour of the RF currents on the plane. If those dumb electrons aren't given a real obvious route to follow, a big wide freeway where they are able to rush down without getting into one of those phantom traffic jams where the traffic just seems to pile up for no particular reason except for weight of traffic - yes, all the physics of freeways applies to electrons too! So what happens in the picoseconds after your 'pond-drop' then becomes more significant - as oscillations set in across the plane, they will then cause degradations in the digital signals, pulling the signals up or down a little so as to reduce the s/n.

Therefore, adding 'splits' in a ground plane is not something to be considered in isolation to the rest of the board design, and EMC components - if it diminishes the impedance to source/sink then it may lead to resonances that may be more degrading on the digital signal than just the initial analogue pulse alone. There again - it might not be! At least your friend's analogy should give you an insight into where and why EMC capacitors might be best located, and to keep fast switching close to the source and sink [viz. shortest loops with the smallest internal area 'within' the loop].

 

[yungman]

I would also regard the 'pond ripple' analogy to be reasonable, but also that it is incomplete. When a switch opens up, it is allowing electrons to flow. That flow is motivated by a difference of potential between one location and another. The question, then, is whether the current is motivated by a potential some distance away, or a potential right next to that space. Logically it is the latter. Electrons will move locally, then further electrons will flow into the space they've left behind. They don't all flow like soldiers on parade, all at once to the sound of someone shouting an order, they flow like cars pulling off from traffic lights with each responding to the one next to it.
But it is really the EM wave propagate out, the electrons really do not move as they are moving at many dimensions slower.
This is why you get overshoot, similarly. The electrons are all racing forwards and the switch is thrown open and they all crash into the back of each other like tailgaters on the motorway. They're real dumb, those electrons! Not a single brain cell between them!

OK, so what bit is incomplete? Well, this all happens on a timescale so short, relative to a PCB, that you're talking nanoseconds and miniscule levels of charge. If this was the only effect, it'd not be very significant.

But the thread so far has generally missed a discussion on the impedance of the circuit back to the sink/source. This is what will dominate the behaviour of the RF currents on the plane. If those dumb electrons aren't given a real obvious route to follow, a big wide freeway where they are able to rush down without getting into one of those phantom traffic jams where the traffic just seems to pile up for no particular reason except for weight of traffic - yes, all the physics of freeways applies to electrons too! So what happens in the picoseconds after your 'pond-drop' then becomes more significant - as oscillations set in across the plane, they will then cause degradations in the digital signals, pulling the signals up or down a little so as to reduce the s/n.

Therefore, adding 'splits' in a ground plane is not something to be considered in isolation to the rest of the board design, and EMC components - if it diminishes the impedance to source/sink then it may lead to resonances that may be more degrading on the digital signal than just the initial analogue pulse alone. There again - it might not be! At least your friend's analogy should give you an insight into where and why EMC capacitors might be best located, and to keep fast switching close to the source and sink [viz. shortest loops with the smallest internal area 'within' the loop].

I am curious about this whole thing but my grandson is here and I have to go out. So I just response to one point first.

I want to make sure you are talking about the case of having both power and ground plane. The case with only ground plane and a power trace is very obvious even in the one shot case because the EM wave can only propagate in a guided structure which is the power trace on top of the ground plane. There will be not rock into a pond at all. All you get is the current density on the ground plane follow the power trace. This is what I refer to as microstrip.
So for two plane case, how do you explain in terms of EM wave as this is really what is happening. I have no idea.

Yes I do agree with you for the single event that it is not obvious that the front of the EM wave see equal potential in all direction ( as it is equal potential at all points between the two planes before the event happen). Therefore the EM wave do not see the source potential from far away. EM wave only see the immediate surrounding and is equal in all direction. It is only want you establish a steady state before you can see the source point as the surface current desity due to the H field establish a slight potential difference along the path.

I still believe even when the EM wave propagate out like rock into a pond at the begining, it will die down fast as the energy of the single di/dt event is finite, so the energy of the EM wave at a given point has to decrease with distance.

 

[Greg-ulate]

Hi everyone, I just discovered this forum. I am very interested by this topic and pleased by the depth of the resulting discussion. I remember when it dawned on me that current should travel back along a path under a trace like a stripline, it was a great step forward for me.

I wouldn't say that I'm incredibly knowledgeable about this, but I see it like this: the most important thing is the speed of light. Because of relativistic effects, accelerating charges "induce" the opposite motion in other nearby charges. This is responsible for what we observe as Magnetic Coupling. The result is exactly what has been stated by the others who have replied: in the case of a ground plane and a power trace, an EM spike caused by very fast switching will move back along the supply trace together with a mirror image traveling with it along the ground plane to the source.

So what happens if there is a slot or gap that disrupts the path of the mirror image current, which wants to follow as close as possible to its twin on the supply trace? It kind of has to take a detour around the gap, trying to get to the other side of the gap so it can rejoin its mirror image on the supply trace, possibly trespassing where it doesn't belong. Also, since now that current is not traveling with an equal and opposite wave on the other side of the board, it radiates! That is bad news. I can see why experienced designers like those who have commented on this post avoid discontinuous ground planes.

Concerning the ripples in a pond part of the question, I do believe that a wave will emanate front the plus and minus pins just like ripples in a pond, BUT(!) since you are a very smart designer and you have put a bypass cap as close as possible to the supply pins, due to the fact that the cap represents a small impedance, when the wave reaches the short distance to the cap a negative reflection of the ripple is superimposed on top of the original, almost completely neutralizing it. The closer the cap is to the pins, the better, because the points of origin will be closer in space and time. I imagine that is why you are unlikely to observe any evidence of that ripple like effect.

I've never used more than a 2 layer board for my designs but I am going to favor 4 layers from now on due to the comments that others have left here, which have definitely helped my understanding of this. (I am still going to separate AGND and DGND with a thin trace or choke though, as per manufacturer's recommendations.)

Here's a question: if you had to chose which section you put closest to an off-board connection to a power supply, would you put it closer to the analog or digital section? I think digital?

 

[yungman]

Well come to the Physics forum.

I think in ideal condition, separate ground has the advantage. But like what you said about a slot, if anyone want to do separate ground, they better like at each trace inch by inch on the layout to make sure there is no cross over the the other ground. My experience it is much more difficult said than done. Books show an IC with digital and analog side separated nicely. But in real life, you have a bunch of ICs that have AGND, DGND, AVcc and DVcc. try cutting the ground plane is more difficult than you think and on top your digital and analog traces has to run on top of their corresponding ground. I layout all my own critical boards, don't listen to me, just do one!

Particular I described in detail about the image current stay right under the trace, you separate by a few trace width ( depend on the thickness of the dielectric), you hardly get any interference. Why do I want to separate the ground?

My posts all assume at frequency that even the 0.01uF bypass cap is running out of steam. So I don't not assume a well placed bypass cap will solve everything. As you can see the current path get complicated on those with power and ground plane. My way of dealing with this is place the two planes only 5mils apart to increase the capacitance so it pickup where the 0.01uF cap poop out. Also for RF amplifiers, I actually put a copper pour on the Vcc pin on the side that is on top of the ground plane and literally create a parallel plate cap just for that IC. I don't trust the 0.01uF cap.

 

[cmb]

the EM wave can only propagate in a guided structure which is the power trace on top of the ground plane. There will be not rock into a pond at all. All you get is the current density on the ground plane follow the power trace. This is what I refer to as microstrip...when the EM wave propagate out like rock into a pond at the begining, it will die down fast as the energy of the single di/dt event is finite, so the energy of the EM wave at a given point has to decrease with distance.

yungman, I think the element in need of discussion here is your perception of 'a propagating wave'. Within the planes of a PCB, they may act as a waveguide, but most certainly not a propagating wave. EM energy within a waveguide may propagate in several possible modes, maybe even several such modes together. This is a combination of currents and magnetic fields, the magnetic fields, obviously, within the space between planes but the currents are real, physical surface currents on the conductors, and are the current under discussion when it comes to talking about what RF currents are present on planes. (Currents, which I may add, do not simply disappear at the plane edge but are variously reflects and/or are carried over onto the other side of the plane - which might then be a radiating surface if it is the last one in the stack.)

Your latter point is all-important. A system in which such guided waves do not damp quickly may result in evident interference. A single solitary pulse that damps/dumps its energy straight to ground might [if that is possible], in theory, have an interfering effect but I think it is unlikely in the most part (for what we'd regard as 'consumer' level electronics).

Mirror currents between planes, or a plane and a track, therefore need to dissipate promptly. The interference comes when those mirror currents are inhibited by impedances back to its source (they are currents on the circuit associated with that part). If they do not, then that energy may bounce around for a while, generating interference at any resonant frequencies associated with it bouncing around, which would be a function of the geometry/termination impedances.

Therefore, these surface currents may, harmlessly, appear on either the analogue or digital planes [and also to note - either on +ve or -ve planes] providing those planes have low impedance to source. IF surface currents appear on a plane or a track that is not connected to source by a low impedance - particularly for example a signal track (analogue or digital) that terminates in some form of detector circuit - then that energy in that impromptu waveguide is likely to bounce around for a while with nowhere to sink to.

A big problem with all this is that at very high frequencies, of the order of board-dimension wavelengths, a 'simple' direct DC low resistance to source may not be enough to prevent resonances. The reason decoupling capacitance might then help might, alternatively [rather than simply regarded as 'high-pass coupling'], be seen to be tuning the frequencies such that the resonances of the board do not match up with frequency content of any likely induced surface currents.

It should not be a surprise, then, that PCB EMC can easily enter the world of the 'dark arts' if the basics have not been got right in the first place, because a failing board might be made to work again with a little nibble of a plane here, a little thicker track there, or a new component value, and although computer simulations have come a long way such subtleties are usually not well-simulated.