- #1
j777
- 148
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Hello,
I'm using an Altera Max II CPLD to interface with a general purpose bus with 60ns bus cycles. This is my first time using programmable logic so go easy on me. Is the required clock for the CPLD usually provided from an external source or can it be generated internally? Is a clock provided externally and then divided or multiplied internally to the desired frequency? I have a 14.7456Mhz clock being fed into the CPLD but I think I need something faster to interface with the bus. Any information related to these questions is appreciated.
Thanks
I'm using an Altera Max II CPLD to interface with a general purpose bus with 60ns bus cycles. This is my first time using programmable logic so go easy on me. Is the required clock for the CPLD usually provided from an external source or can it be generated internally? Is a clock provided externally and then divided or multiplied internally to the desired frequency? I have a 14.7456Mhz clock being fed into the CPLD but I think I need something faster to interface with the bus. Any information related to these questions is appreciated.
Thanks