Partial address decoder interfaced 68000-based system

[Johnny99]

Homework Statement

A circuit containing 24KB RAM is to be interfaced to a 68000-based system,so that the first address of RAM (the base address) is at $002000.
(a)What is the entire range of RAM addresses?
(b)Design a PARTIAL address decoder using three 8KB RAM ICs.

2. The attempt at a solution

for question (a) my answer is:
The address range for the RAM is from $002000 to $002000+(24K=24*2^10=24576=$006000)=$008000-1=$007FFF

Now I got problem for solving question (b).If I want to divide the address range ($002000 - $007FFF) into 3 (because of 3 8KB RAM), it will be
($002000-$003FFF) for RAM A
($004000-$005FFF) for RAM B
and
($00600 - $007FFF) for RAM C.
Each one 8KB RAM has address A0-A12
68000 does not contain A0 ,it only contain UDS*/LDS*.My question is, can I just interface address bus A1-A13 of 68000 to A0-A12 of RAM and not include UDS*/LDS*? .I 'm afraid it will be wrong because I have encountered example in the book which almost same with this question but it has 2 8KB RAM,it use UDS*/LDS* as chip select and lower byte will be in one RAM upper byte in another.

 

[KataKoniK]

I would suggest that you first review the datasheets for the 68000 and the 8KB RAM ICs to understand their address and data bus configurations. This will help you determine the best way to interface them and design the address decoder.

In general, the UDS*/LDS* signals are used to select the upper or lower byte of data on the data bus, depending on the address being accessed. So in your case, you can use the address bus A1-A13 to address the 8KB RAM ICs, and use the UDS*/LDS* signals to select the upper or lower byte of data. This will allow you to access the full 8KB of each RAM IC.

For the address decoder, you can use a combination of AND gates and inverters to generate the chip select signals for each RAM IC. For example, for RAM A, you can use the address lines A1-A13 and invert them to create the chip select signal for that IC. You can then use the address lines A2-A13 and invert them to create the chip select signal for RAM B, and so on.

I would also recommend simulating your design using a software tool such as Logisim to ensure that it is functioning correctly before implementing it in hardware.

 

[Mene]

I would suggest that you consult with a more experienced engineer or refer to the datasheet of the specific RAM ICs you are using to determine the best approach for interfacing them with the 68000-based system. It is important to carefully consider the timing and signal requirements of both the RAM and the 68000 in order to ensure proper functionality and avoid any potential issues. It is also possible that different RAM ICs may have different requirements for interfacing with the 68000, so it is important to confirm the appropriate approach for your specific setup.