3 input XOR gate using NAND gate only ( Logic )

[i_madini]

We can use NAND gate only to get ( XOR gate ) of 2 input ( A and B ) :

By using (4) NAND gate :

The output of 1'st NAND : (AB)'

The output of 2'nd NAND : ((AB)'.A)' = (A'B)

The output of 3'rd NAND : ((AB)'.B)' = (AB')

The output of the hole circuit will be: ((A'B).(AB'))' = AB' + A'B ( Which is an XOR gate )

The truth table of ( XOR gate ) is:

00 0
01 1 A'B
10 1 AB'
11 0

What about in case of 3 input ( A, B, and C ) ?!

I Know the output should be by using (8) NAND gates :

000
001 (A'B'C)
010 (A'BC')
011
100 (AB'C')
101
110
111 (A'B'C')

Y= (A'B'C)+(A'BC')+(AB'C')+ (A'B'C')

But how to drive it ? I mean the output at each NAND ?


Any HELP !

 

[aralbrec]

Y= (A'B'C)+(A'BC')+(AB'C')+ (A'B'C')

But how to drive it ? I mean the output at each NAND ?

I am going to tell you a secret that I haven't seen formally taught in textbooks. I'd like to hear if anyone knows differently.

It's about understanding active high and active low logic.

A NAND gate, when drawn, looks like an AND with a bubble on the output. This is because it takes two active high inputs (no bubbles), ANDs them and generates an active low output (a bubble). Active high means 1s are high voltage and 0s are low voltage. Active low means 1s are low voltage and 0s are high voltage. You can see this from the truth table, which works on voltages:

A B NAND
0 0 1 (0 active low)
0 1 1 (0 active low)
1 0 1 (0 active low)
1 1 0 (1 active high)

See how it's just a straight AND gate if you interpret the output voltages as active low logic? So when you draw the NAND circuit symbol, you can interpret it as performing AND with active high inputs and active low outputs.

We can also apply DeMorgan's Law to a NAND gate. !(A AND B) = !A OR !B

The meaning of this: take two active low inputs OR together to make an active high output.

We're still using the NAND gate to implement this function so we still have the same truth table but this time we are going to interpret the high and low voltages differently:


A B NAND
0 (1 active low) 0 (1 active low) 1 (active high)
0 (1 active low ) 1 (0 active low) 1 (active high)
1 (0 active low) 0 (1 active low) 1 (active high)
1 (0 active low) 1 (0 active low) 0 (active high)

Just by interpretting the inputs to the NAND gate as active low and the output as active high, using the *same* gate we have found an OR function.


The last missing ingredient is an inverter, which is simply tying both inputs together (check with a truth table).


So now with a NAND gate we can make inverters, OR, AND if we interpret the voltage levels appropriately (active high or active low) and this can be summarized with graphical circuit symbols.

AND:

Draw an AND gate with no bubbles on the input and a bubble on the output (ie the usual NAND symbol). The interpretation is active high inputs are ANDed together to form an active low output.

OR:

Draw an OR gate with bubbles on both inputs and no bubble on the output. The interpretation is two active low inputs are ORed together to form an active high output.

NOT:

Draw like a regular inverter. The inverter is the same in active low or active high logic; you can draw the bubbles on either side of the buffer symbol.


It may sound confusing at first but an actual application will show how easy it is. The implementation strategy being used is called pushing bubbles around the circuit.

Your equation:


Y= (A'B'C)+(A'BC')+(AB'C')+ (A'B'C')

We are ORing together four things. You only have two input NAND gates so you need to use two gates to OR two things and then another gate to OR the results together. A nand OR gate looks like an OR gate with bubbles on the input and no bubbles on the output. I have attached a really bad drawing of four terms A,B,C,D being ORed together using NAND gates.

The top drawing, I have not connected the last OR gate because there is an active high / active low incompatibility. The outputs from the first OR gate are active high but the inputs to the last OR gate are active low. So what I did was push the bubbles through the first OR gates to make a NAND gate with a bubble on the output. Now I can connect that last OR gate because the logic levels are correct. Changing the OR to NAND is allowed because the same NAND gate does both, logically; in the process of changing the symbol I have changed the inputs to active high logic. But I need the inputs to be active low to implement the correct function. So I have put bars over them to indicate they are active low. The bars can indicate /A active high or A active low.

See if you can proceed from there and fill in the rest for A,B,C,D.

 

[i_madini]

Thank you, Sir.

I really appreciate it ..

And that little secret is so helpful to switch between gates ..

But what I'm interesting in is to find the output at every single NAND gate ..

Starting from X1, X2, X3, X4, X5, X6, X7, and Y.

These X's is shown in attachment.

I'm stuck at,

X5: (( AB' + A'B ) . ( C ) )' = ?


Again, Thanks a lot.

 

[aralbrec]

I thought you were trying to implement a three input XOR gate from your truth function using NANDs? Y= (A'B'C)+(A'BC')+(AB'C')+ (A'B'C')

Or are you trying to analyze your circuit? With your circuit I can see the same gates are repeated from X5 on. So if up to X4 is XOR, then the whole thing is XORing three inputs. I'd slice the circuit after X4, show what the output to X4 is, see that X5 on is the same function and put them together.

I see you have a NAND implementation for XOR of two inputs...you can always use three XOR gates to implement XOR for three inputs but the implementation won't necessarily be optimal.

 

[rezeew]

I would first like to commend you on your creative use of NAND gates to create a 3-input XOR gate. This is a great example of using logical thinking and problem-solving skills in circuit design.

To answer your question about how to drive the output at each NAND gate, we can look at the truth table for a 3-input XOR gate:

A B C | Y
0 0 0 | 0
0 0 1 | 1
0 1 0 | 1
0 1 1 | 0
1 0 0 | 1
1 0 1 | 0
1 1 0 | 0
1 1 1 | 1

From this truth table, we can see that the output Y is 1 in four cases (when A=0, B=1, C=0; A=0, B=0, C=1; A=1, B=0, C=1; A=1, B=1, C=0) and 0 in the other four cases.

To drive the output at each NAND gate, we can use the following logic:

For the first NAND gate, the output will be (A'B'C)' since it is the inverse of the first row of the truth table (when Y=0).

For the second NAND gate, the output will be ((A'B'C)'.A)' = (A'B) since it is the inverse of the second row of the truth table (when Y=1).

For the third NAND gate, the output will be ((A'B'C)'.B)' = (AB') since it is the inverse of the third row of the truth table (when Y=1).

For the fourth NAND gate, the output will be ((A'B'C)'.C)' = (A'B') since it is the inverse of the fourth row of the truth table (when Y=0).

For the fifth NAND gate, the output will be (((A'B'C)'.A)'.B)' = (A'B'C) since it is the inverse of the fifth row of the truth table (when Y=1).

For the sixth NAND gate, the output will be (((A'B'C)'.A)'.C)' = (A'BC') since it is the inverse of the sixth row of the truth table (when Y=0).

For