Register to reply

LTSpice Clock signal distortion

by salil87
Tags: clock, distortion, ltspice, signal
Share this thread:
salil87
#1
Dec14-13, 01:15 PM
P: 27
Hi
I made a counter using Dflop in Ltspice. But when I am using the count bits as signal to other circuits the clock signal is getting distorted. Why is this happening? How can I overcome this problem?
Thanks
Salil
Phys.Org News Partner Engineering news on Phys.org
Researchers discover cool-burning flames in space, could lead to better engines on earth (w/ Video)
Professors object to FAA restrictions on drone use
UConn makes 3-D copies of antique instrument parts
analogdesign
#2
Dec14-13, 01:23 PM
P: 474
You might be loading the Dflops too much. Try putting buffers between the counter output bits and whatever circuit they are driving.
jrive
#3
Dec16-13, 08:43 AM
P: 40
can you post your LTSpice schematic and results showing the distorted clock?


Register to reply

Related Discussions
How does a clock signal function Electrical Engineering 1
Relating phase noise & jitter of clock signal Electrical Engineering 0
Digital Communications : Distortion signal Calculus & Beyond Homework 2
AC+DC signal equation=> Then Filter AC signal= output only DC signal visible Engineering, Comp Sci, & Technology Homework 10
Signal Distortion Introductory Physics Homework 2