NAND or NOR Logic Gate, which is less reliable at higher speeds

[AlmostDone25]

Trying to find out information on NAND and NOR logic gates and which, if any, may be less reliable at higher speeds. Supposedly this would have something to do with propagation delays and triggering times.

 

[berkeman]

I don't know the answer, but here's some wiki background on the basic structures:

http://en.wikipedia.org/wiki/NOR_gate


[EDIT -- removed my incorrect guess at the answer]

 

[chroot]

The NOR gate has a higher logical effort than the NAND (5/3 versus 4/3 for a 2-input gate), and thus is slower. I don't know what exactly you mean by "reliability" at high speed, but the NAND gate is faster.

- Warren

 

[es1]

I haven't seen the notation "5/3 versus 4/3" before. What does it mean?

 

[chroot]

The logical effort of a gate is basically the product of its input capacitance and drive resistance, divided by the input capacitance and drive resistance of an inverter, which is used for reference.

$h = \frac{{C_{in,gate} \cdot R_{drive,gate} }} {{C_{in,inverter} \cdot R_{drive,inverter} }}$

The typical inverter has an input capacitance of 3 units, since the PMOS is typically twice the size of the NMOS. The inverter's drive resistance is taken to be 1, and thus the bottom of the fraction is always 3.

To achieve the same drive strength as the inverter, the 2-input NAND must have an input capacitance of four units (as seen by each input), and thus its logical effort is taken to be 4/3. The 2-input NOR has an input capacitance of five units (as seen by each input) and thus its logical effort is taken to be 5/3.

More complex gates necessarily have more input capacitance than the inverter, and thus are slower, given identical output drive strengths. Logical effort captures this in a single number; gates with higher logical effort are slower.

- Warren

 

[es1]

Got it. Thanks chroot.