# A positive peak detector circuit

by FOIWATER
Tags: circuit, peak, positive
 PF Gold P: 372 meBigGuy, do you have any suggestions for how I should monitor diode current during reset..
P: 1,074
 Quote by FOIWATER meBigGuy, do you have any suggestions for how I should monitor diode current during reset..
I thought multisim would let you monitor currents. If not, you can insert a small resistor and measure the voltage across it.

I just thought of a problem with using an emitter follower, which is that when the input signal goes below the peak the opamp output goes to -5, and the peak voltage is on the emitter, back biasing it and possibly breaking it down. There are other ways to buffer the output, if that is what's needed.

As for the reset, we will see how much current is being drawn. You could put a series resistor in series with the discharge fet to limit the current. Or, you could disconnect it when you reset it (with a FET to ground that opens when you reset).

I see the slew of AD829 is 150V/us with a 500 ohm load , but short circuit current is only 32ma.

I think your slew rate is actually a bit higher than you calculated. The fast section of a sine wave is about 1/3 the period, so for a 500Khz that is 2uS/3 = ~700ns. 10V/700ns is 14V/uS.

14V/uS across .002uF (i = Cdv/dt) = .002uF*14V/uS = 28ma. I don't think the amp can drive its short circuit current actively (not sure) so it may be current limiting.

Try reducing the capacitor until the slew problem goes away. .001 might be low enough (just to test this theory).
 P: 1,074 Have you looked at using an LF398? It has a slow acquisition time, but that may not be an issue in track and hold. You can use a comparator to stop sampling when the input drops below the output.
 PF Gold P: 372 You are right that reducing the capacitor solves the slew problem, however, it overcharges on the rising edge and picks up a positive peak detection which is inaccurate. I will run a simulation and post back with the results you asked for tonight, I appreciate the help.
 P: 1,074 The over charging may be due to the lag caused by the resistance of the diodes, or maybe an effect of the diode biasing amp. Not sure.
P: 1,803
Attached is a circuit that could be a starting point. The circuit is not optimized and differs from yours in many ways. I'm sure it can be made simpler. However it does seem to work, at least with LTSPICE.

Included are the schematic, the netlist and a section of the plot. In the plot, the green trace is the 1 Vpk sinewave at 5 MHz and the blue trace is the peak voltage which is held for 0.1uS before it is reset. Despite its value of only 240pF, the capacitor's voltage doesn't seem to droop.
Attached Thumbnails

Attached Files
 Peak Detector Netlist.txt (594 Bytes, 2 views)
 PF Gold P: 372 meBigGuy - I am starting to think it's the diode as well... Skeptic, nice job..... Personally I am trying to get this to work with the AD829, since as meBigGuy stated previously the circuit shouldn't really be out of the range of this device. Skeptic, what kind of waveforms do you get for voltages between 20mV, to about 2.5 volts? how about frequencies between 10kHz and 500kHz? These are the limits I have set for myself, Are they (in your opinion) attainable?
 PF Gold P: 372 I have added the BJT for current gain, it did not reduce the slew rate problem exactly, I also replaced the AD829 with a LM311 comparator. notice the pics attatched, the low voltage low frequency is still overcharging, while for high frequencies it is undercharging. I also built this circuit and scoped it. What a mess! Attached Thumbnails
 P: 1,074 1. In the high frequency plot you can see that when the discharge FET turns off it dumps negative charge into the capacitor (through gate-drain junction). The discharge FET comparator needs to be biased such that it can turn off slowly before the 0 crossing (or use a FET with less gate-drain capacitance). You need to slow down the switching signal. A way to test it is to add a capacitor on the output of the comparator to slow it down. Also, if you probe the gate and drain at the same time you will see the similarity. 2. The low frequency plot is trying to reach 5V, but it can't get there because there are 3 diode drops. Try only driving to 2.5V and see what it does. BTW, the same spike at the 0 crossover will be there in low frequency mode, but you just don't see it. 3. Replace the second diode with the emitter follower. 1 diode, 1 emitter follower (which is a diode). 4. The feedback *has* to go to the capacitor. That's a must. If the leakage is too much, then you have a problem and need to change to a cmos opamp. That in itself may be the reason an AD829 is not a good choice. But, if we can get the emitter follower to work you can increase the capacitor.
 PF Gold P: 372 OK I got rid of the 2nd diode, I see it isn't necessary not sure what I was thinking, With the emitter follower I get some, weird waveforms lol I will post in the AM. Thanks for the feedback. What do you mean about the feedback having to go to the cap?
 P: 1,074 The feedback to the input op-amp has to come from the storage cap not the base of the follower. The goal is for the voltage across the cap to equal the input voltage. There is another approach to this that eliminates the reset FET. Look at the LF398. You need logic to determine when to sample though. Open the switch when the input drops below the output. Once the input crosses 0 you just close the switch. As with any sample and hold you always have to deal with charge injection when you switch the FET (as you saw)
 PF Gold P: 372 For anyone interested, the attached circuit performs to spec, uses both an AD829 and LM318 with the same basic config as discussed. Any one have any possible improvements? (The main drawback I was not considering was compensation caps for the op amps, which I got from the data sheets) Attached Thumbnails
 P: 1,074 Looks pretty cool. Post some waveforms. Are you saying the 829 compensation solved the slew rate problems? I have questions (curiosity). Why the resistor in series with the main storage capacitor? What does R5 do? (looks like it is just across the supply)? What does C6 do? How did you choose that?
 PF Gold P: 372 Ill take some pictures of the oscilloscope I have made the circuit it works, pretty decently. Perfectly in the simulator but, yeah. Yeah there is absolutely no slew rate problems with this circuit what so ever. but notice it is being driven at unity gain. The 829 is one of the fewer than 5% of op amps without unity gain compensation. As such it requires external capacitors to ensure it doesn't go unstable. (the stair-casing we saw earlier at unity gain). Usually the compensation capacitor is placed from pin 5 to ground but it worked really good here.. I am still trying to find out why by looking at ad's blog this helped a lot http://www.analog.com/library/analog...e_loading.html R5 is actually a resistor on the output of the 829 which shifts the pole of the op amp due to the internal capacitor. It allows for higher bandwidth R5 just keeps the simulator happy. adds no real effect when breadboarded. Just something I picked up from using multisim
 PF Gold P: 372 (also R5 is not connected to the positive rail, it's from the pins to the negative rail I know it looks like it is though)

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