[verilog] change from always@ to assign

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In summary, the conversation discusses two different codes that are meant to output a recover signal based on certain conditions. The first code (code i) uses an always block while the second code (code ii) uses assign statements. However, the results of the second code are not as expected. The person is asking for help in identifying the issue with the second code.
  • #1
hoheiho
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Homework Statement


Halo, I have written a always@ (code i,pic1) which can output what I want but the result is delayed 1 clock cycle, therefore I have changed it to assign (code ii,pic2)and try to output the recover signal immediately when pcreg_1 is changed. But waveform is not what I wanted. Did I miss somethings in (code ii)? The recover is high in 2 clock cycle and I cannot get 0.

code i
Code: 
always @(posedge clk)
begin
  if (store)
      if (m2==pcreg_1)
        recover = 0;
      else
        recover = 1;
  else
      if (m1==pcreg_1)
        recover = 0;
      else
        recover = 1;     
end

code ii
Code: 
assign recover = (store && (m2==pcreg_1))? 1'b0:1'b1;
assign recover = (!store && (m1==pcreg_1))? 1'b0:1'b1;

Could anyone give me a hand for me :(?

Thank you very much for help
Ivan
 

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  • #2
Did anyone can see what's the problem :(?
 

What is the difference between using always@ and assign in Verilog?

The always@ block in Verilog is used to describe a sequential logic process, where the output is dependent on the current and previous inputs. It is used to model registers, flip-flops, and other sequential elements. On the other hand, the assign statement is used to describe combinational logic, where the output is solely based on the current inputs and does not have any memory.

When should I use always@ and when should I use assign in my Verilog code?

You should use always@ when you need to model sequential logic, such as registers or flip-flops. This is because the always@ block allows you to use non-blocking assignments, which are necessary for proper modeling of sequential elements. You should use assign when you need to model combinational logic, such as logic gates or multiplexers.

Can I use both always@ and assign in the same Verilog code?

Yes, you can use both always@ and assign in the same Verilog code. In fact, it is common to use both in a single module. You can use always@ to model sequential logic and assign to model combinational logic within the same module.

What are the advantages and disadvantages of using always@ compared to assign in Verilog?

The main advantage of using always@ is that it allows you to model sequential logic accurately and efficiently. It also allows for easy simulation and verification of the code. On the other hand, the main disadvantage of using always@ is that it can lead to complex and difficult-to-maintain code if not used properly. Assign, on the other hand, is simple and easy to use, but may not accurately model sequential logic and can lead to race conditions if used incorrectly.

Are there any specific coding guidelines for using always@ and assign in Verilog?

Yes, there are some recommended coding guidelines for using always@ and assign in Verilog. Some common guidelines include using non-blocking assignments in the always@ block, avoiding mixing blocking and non-blocking assignments in the same always@ block, and using assign for simple combinational logic. It is also important to properly document and comment code using always@ and assign for better understanding and maintenance.

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