Inhibiting NAND & NOT Gates - Active High or Low?

  • Thread starter mkbh_10
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In summary, inhibiting a gate means disabling it so that its output remains constant. This can be achieved by tying one input of an AND gate low or one input of an OR gate high. The term "inhibit" may refer to a specific input on these gates, such as "the condition," and the problem may be asking how to build an AND gate using a NAND gate or a NOR gate.
  • #1
mkbh_10
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Homework Statement


How can you inhibit NAND & NOT gate ? Mention whether the inhibit is active high or active low ?


Homework Equations





The Attempt at a Solution



No clue to this question
 
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  • #2
What does it mean to inhibit a gate?
 
  • #3
i myself don't know ? there are 16 boolean combinations for a 2 input gate & inhibit is one of them but i don't know more about it
 
  • #4
After some googling, the "inhibit gate" seems to be just an AND gate with one of the inputs called "the condition" or something like that. Perhaps the problem is asking you to build an AND gate from a NAND gate and from a NOR gate.
 
  • #5
"Inhibit" is not a term that most engineers would recognize. I suppose the question is asking "how do you disable a gate, so it's output remains constant."

If you tie one input of an AND gate low, then it's output will always be low, no matter what happens on the other inputs.

If you tie one input of an OR gate high, then it's output will always be high, no matter what happens on the other inputs.

- Warren
 

1. What is the purpose of inhibiting NAND and NOT gates?

Inhibiting NAND and NOT gates allows for control over the output of these logic gates. By inhibiting, the output can be forced to a specific state, regardless of the input.

2. How do you inhibit a NAND or NOT gate?

To inhibit a NAND or NOT gate, a signal must be applied to the input that is the opposite of the desired output. For example, to inhibit a NAND gate from outputting a 1, a 0 must be applied to both inputs.

3. Is inhibiting NAND or NOT gates considered active high or low?

Inhibiting NAND and NOT gates can be considered active high or low, depending on the implementation. Some designs may require a high signal to inhibit while others may require a low signal.

4. What are the benefits of using an inhibited NAND or NOT gate?

Inhibiting NAND and NOT gates can be useful in creating more complex logic functions, such as flip-flops or latches. It also allows for greater control over the output of these gates.

5. Are there any drawbacks to using inhibited NAND or NOT gates?

One drawback of using inhibited NAND and NOT gates is that it adds an additional layer of complexity to the design. It also requires careful consideration of the input signals to ensure the desired output is achieved.

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