Solving Delays in 8:3 Encoder Design with Verilog

  • Thread starter polaris90
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In summary: However, this is not the desired output, as the priority should be given to the higher number inputs.In summary, the conversation is about designing an 8 to 3 encoder using verilog and the discussion is focused on the delays in the output shown in a functional simulation. The reason for these delays is identified as logic hazards, specifically when multiple events occur simultaneously, causing the output to temporarily reach a state that is not desired. Feedback is requested to address this issue and ensure that the priority encoding is functioning correctly.
  • #1
polaris90
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I have a question about encoders. In one of my classes we had to design a 8 to 3 encoder using verilog. my code is the following.


Code:
module encoder( S, D, E);
input E;  //enable
input [7:0] D;  //input x, y, z
output[2:0] S;  //ouput
reg [2:0] S;
always @ (E or D)begin
	if (E==1) begin
	case (D)
	8'b00000001 : S = 3'b000;
	8'b00000010 : S = 3'b001;
	8'b00000100 : S = 3'b010;
	8'b00001000 : S = 3'b011;
	8'b00010000 : S = 3'b100;
	8'b00100000 : S = 3'b101;
	8'b01000000 : S = 3'b110;
	8'b10000000 : S = 3'b111;
	default :S =3'bx;
endcase
end
end
endmodule

I simulated my encoder using a functional simulation and the output is shown in the picture attached. I see that there are many delays in the output(shown my the glitches in the graph). My question, is why are these delays really produced. When looking at the logic circuit, every output corresponds to 8 inputs, in which one of them is a 1. I see it's a single step with only one gate delay unless I'm wrong. Then when looking at the priority encoder the delay seems to be higher. Could someone give me some feedback on this?
 

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  • #2
The simulator is identifying logic hazards.

For example at 20ns we have three events occurring simultaneously:
D[5] rising, D[6] falling, and D[7] falling.

The simulator is showing you that during this transition, the state: D[5] low, D[6] high, D[7] low may be reached, even if very briefly, causing S[0]=low.
 

1. What is an 8:3 encoder?

An 8:3 encoder is a digital circuit that takes in 8 input signals and produces 3 output signals. It is used to compress data by selecting the active input and encoding it into a binary format.

2. What are the common delays in 8:3 encoder design with Verilog?

The common delays in 8:3 encoder design with Verilog include propagation delay, setup time delay, and hold time delay. These delays can affect the performance and reliability of the encoder if not properly managed.

3. How can delays be solved in 8:3 encoder design with Verilog?

Delays in 8:3 encoder design with Verilog can be solved by using techniques such as pipelining, retiming, and parallel processing. These techniques help to reduce the overall delay and improve the speed and efficiency of the encoder.

4. What is Verilog and how is it used in 8:3 encoder design?

Verilog is a hardware description language used for designing digital circuits. It is used to describe the behavior and structure of the 8:3 encoder, allowing the designer to simulate and verify its functionality before implementation.

5. Can Verilog be used to design other types of encoders?

Yes, Verilog can be used to design various types of encoders such as priority encoders, decimal encoders, and octal encoders. It is a versatile language that can be used for designing a wide range of digital circuits.

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