Turning FETs off in presence of AC signal at Drain or Source

In summary, the problem is that the parasitic caps (and perhaps the parasitic internal BJT) on the FETs, configured as 2 back-to-back N-channel mosfets to block any current flowing through the body diodes, cause current to flow through the FETs. This is necessary so that the reflected load back onto the primary is minimized. The objective is to be able to turn mosfets M1 and M2 FULLY OFF such that current in the secondary is minimal so that the reflected load back onto the primary is minimal as well.
  • #1
jrive
58
1
Turning FETs "off" in presence of AC signal at Drain or Source

Hello,

I have a very interesting problem that surprised me, and as of yet have not been able to find a solution for.

I have two coupled coils. One is being driven by a pulses. The other coil has FET switches to switch the high load path out and instead divert the induced current through a lighter load. This is necessary so that the reflected load onto the primary is minimized. The problem is that the parasitic caps (and perhaps the parasitic internal BJT) on the FETs, configured as 2 back-to-back N-channel mosfets to block any current flowing through the body diodes, cause current to flow through the FETs (remember, the voltage at the node between L2 and R2 is positive and negative). So, I cannot fully turn the FETs off, and the load on the undriven coil is not the 100k, but the 100K in parallel with the 75ohm plus the parasitic impedance presented by the FETs.

I've tried other switching elements, but I still can't get this to work. I can't use a relay (which would work fine, by the way).

So, I'm stumped. Any suggestions are welcome. Again, the objective is to be able to turn mosfets M1 and M2 FULLY OFF such that current in the secondary is minimal so that the reflected load back onto the primary is minimal as well.

Thanks!
 

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  • #2


Are you really using 2 NMOS in series just so that their body diodes oppose each other or did I read your description wrong? When you say high load and light load, do you mean in terms of current draw or current resistance? The bottom FET should never turn on as its Vgs (-5V) is always less than threshold voltage, and so I don't see the purpose of having it there.

Also, how high is the voltage being produced across the FETs and is this less than the Vds breakdown voltage such that you're not seeing leakage current?

Have you considered using a series resistor to impede the AC component? You could also rearrange your 100k and FETs so that the two loads are switched, rather than relying on one to shunt the other. Also, have you read about resonant switches? I'm not sure if looking into that would help or not, but a ZVS switch can use your parasitics to an advantage to switch at a specific time (it will hold at least twice the voltage across Vds though).
 
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  • #3


Yes, so that their body diodes oppose each other. The polarity of the node above upper FET goes above and below ground (in fact, +/-3V) and if I were to have just the one FET, current would flow the the diode of the FET in the one direction.

Neither FET should ever turn on, that's the point. Both have negative Vgs at all times. Even the top FET has a -2Vgs worst case.

"Have you considered using a series resistor to impede the AC component? " --> I'm only showing part of the circuit/logic in the diagram. I need to switch the load between 75 ohms and 100k under different conditions on the secondary side. The problem lies when I try to switch the light load (100K), since it is always in parallel with the load presented by the "not-completely-off" FETs.

I have not read into resonant switches; I'll take a look.

Thank you!
 
  • #4


jrive said:
Yes, so that their body diodes oppose each other. The polarity of the node above upper FET goes above and below ground (in fact, +/-3V) and if I were to have just the one FET, current would flow the the diode of the FET in the one direction.

Neither FET should ever turn on, that's the point. Both have negative Vgs at all times. Even the top FET has a -2Vgs worst case.

"Have you considered using a series resistor to impede the AC component? " --> I'm only showing part of the circuit/logic in the diagram. I need to switch the load between 75 ohms and 100k under different conditions on the secondary side. The problem lies when I try to switch the light load (100K), since it is always in parallel with the load presented by the "not-completely-off" FETs.

I have not read into resonant switches; I'll take a look.

Thank you!

I'm not sure if a resonant switch would help or not, as they are designed to use resonance to turn on. But it sounds like you need some kind of dummy reactive load or a resistance in series with your switch to impede the AC signal. I'm just trying to offer shotgun approach to your problem since I don't know all of the conditions that you expect your circuit to be in (I don't know what values your gate voltage source could be switching between for example) nor do I know the application.

I don't think the back to back NMOS is such a good solution for your body diode issue, but that's my limited experience opinion.

You did not mention what size FETs you are using. If they are power FETs they will have worse junction parasitics, and you could switch to smaller FETs if the conditions allow.
 
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  • #5


jrive said:
I have a very interesting problem that surprised me, and as of yet have not been able to find a solution for.
You're troubled by significant capacitance between D and S, effectively bypassing your schematic's [ideal] FET? Would a diode switch be a feasible alternative? What is the peak current through the 75Ω?

You show a 100k load. If you were to come up with a switch with an OFF resistance of 100k could you accommodate it by replacing your 100k resistor with 200k (giving an overall load of 100k)?
 
  • #6


Have you now solved this, or do you want me to sketch a diode switch arrangement?
 
  • #7


Although i can't use diodes because of their variations with temp, i'd like to still seea sketch of the diode switch solution.

To comment on you other suggestion, when the 75 ohms are switched into the circuit, i need the switch's on resistance to be neglible relative to the 75ohms (with the FETs, we're talking 10s to 100s of milliohms.)

Thank you,
 
  • #8


Where the earthy end of the coil can be isolated from DC earth, it allows the injection of DC. When heavily forward biased the diode is a low impedance, when reverse biased is just a few pF to ground.
 

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1. Why is it necessary to turn off FETs in the presence of an AC signal at the Drain or Source?

Turning off FETs in the presence of an AC signal is necessary to prevent damage to the device and ensure proper functioning. AC signals can cause excess current to flow through the FET, leading to overheating and potential failure.

2. What are the potential consequences of not turning off FETs in the presence of an AC signal?

If FETs are not turned off in the presence of an AC signal, it can lead to overheating, excessive power dissipation, and ultimately failure of the device. It can also result in distortion of the AC signal and affect the performance of the circuit.

3. How do you turn off FETs in the presence of an AC signal at the Drain or Source?

FETs can be turned off in the presence of an AC signal by applying a negative voltage at the Gate terminal. This negative voltage creates a reverse bias between the Gate and Source, effectively turning off the FET and preventing current flow.

4. Are there any specific considerations when turning off FETs in the presence of an AC signal?

Yes, it is important to consider the amplitude and frequency of the AC signal, as well as the gate voltage and capacitance of the FET. These factors can affect the speed and efficiency of turning off the FET and should be taken into account for optimal performance.

5. Can FETs be turned off while an AC signal is still present at the Drain or Source?

Yes, FETs can be turned off while an AC signal is present, as long as the gate voltage is sufficient to create a reverse bias. However, it is recommended to turn off the FET before the AC signal reaches its peak amplitude to prevent high currents and potential damage to the device.

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