Is it possible to have a positive or negative edged J-K master slave flip flop?

In summary, it is possible to have an edge triggered J-K master slave flip flop, where either the master or the slave is positive or negative edge triggered. The equation for the inputs is derived from the timing diagram and the output is asserted on either the rising or falling edge of the clock cycle. The design implementation for this type of flip flop will depend on its timing diagram.
  • #1
Amith2006
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Homework Statement


Does an edge triggered J-K master slave flip flop exist? In a clocked J-K master slave flip flop, the master may be positive edge triggered and the slave may be negative edge triggered or vice versa. Can this flip flop be called an edge triggered J-K master slave flip flop?If so,is it positive edge triggered or negative edge triggered?Then what about the truth table? In the column of clock in the truth table, should a pulse symbol or positive edge or negative edge be drawn?



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  • #2
... you forgot section 3.
 
  • #3
whoa hold on there that's a lot of questions in one.

Basicly it is possible to have either a positive or negative edged flip flop. The equation for the inputs is derived from the timing diagram. If an output is asserted on the falling edge of the flip flop its negative edge triggered (as it goes from positive to negative) - else its asserted on the rising edge of the clk cycle and its a positive edged triggered flip flop

So how are these questions dealt with ?

Heres an example i posted earlier.
not the best example - its all i could find now - but see how the implementation is done - using a timing diagram:

http://img519.imageshack.us/img519/6614/lect3kw5.jpg [Broken]
http://img261.imageshack.us/img261/5708/lect31ry3.jpg [Broken]

so in essence - theoretically a JK flip flop or any flop flop can be edge triggered and its design implementation will thus come from its timing diagram (or take that into account)
 
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1. What is a J-K master slave flip flop?

A J-K master slave flip flop is a type of sequential logic circuit used in digital electronics. It consists of two interconnected D flip flops, where one acts as the master and the other as the slave, allowing for the storage and transfer of data.

2. How does a J-K master slave flip flop work?

A J-K master slave flip flop works by using the inputs J (set) and K (reset) to control the output state. When both inputs are low, the current state is maintained. When J and K are both high, the outputs will toggle, and when J and K are different, the output will either set or reset to the corresponding input.

3. What are the advantages of using a J-K master slave flip flop?

One advantage of a J-K master slave flip flop is its ability to eliminate the race conditions that can occur in other types of flip flops. It also has a more predictable output, making it useful for applications that require precise timing.

4. What are some common applications of J-K master slave flip flops?

J-K master slave flip flops are often used in synchronous circuits, counters, and frequency dividers. They can also be used in memory circuits and state machines.

5. What is the difference between a J-K master slave flip flop and other types of flip flops?

The main difference between a J-K master slave flip flop and other types of flip flops is its ability to toggle the output when both inputs are high. This feature allows for more flexibility in designing sequential logic circuits and eliminates potential problems such as race conditions.

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