Simulating a NAND/AND gate in Emitter Coupled Logic?

In summary: Basically the principle is that of a differential amp/long tailed pair configured as a comparator (eg one input fixed voltage).When you set the voltage levels for the inputs, it's important to make sure that the bias voltage, VBB, is set correctly. VBB is the voltage that tells the logic if an input is "true" or "false".
  • #1
jean28
85
0

Homework Statement


I need to simulate a AND/NAND gate with Emitter Coupled Logic. As I'm sure that most of you know, ECL is mostly used to make OR/NOR gates, so finding out how to make a NAND/AND gate is not as easy as it sounds.


Homework Equations





The Attempt at a Solution



I attached an image of a possible model that I found online. However, how do I know which values I should put in order to make the circuit work? How do I know which voltages should be in VBB1, VBB2, etc?

Thanks
 

Attachments

  • NANDAND.jpg
    NANDAND.jpg
    22.2 KB · Views: 2,013
Physics news on Phys.org
  • #2
jean28 said:
How do I know which voltages should be in VBB1, VBB2
I did a web search and VBB is the bias voltage use to determine if an input is "true" or "false", but I couldn't find the specific voltages.
 
Last edited:
  • #5
jean28 said:
That is for OR/NOR functions.
True, but it does show that VBB for Q3 is -1.29V, while VCC is -5.2V, the same as your AND / NAND circuit. In general, VBB is set to the middle of the .8 voltage difference beween a logic "0" and a logic "1". I found an ECL document that specifies the voltage range for VBB as well as the other voltage ranges:

https://smartech.gatech.edu/jspui/bitstream/1853/32110/1/PG_TR_050518_RJP.pdf
 
Last edited by a moderator:
  • #6
I think it will be slightly different for the NAND because if you follow the path from INB to VBB2 there is an aditional Vbe compared to a NOR. It goes...

INA - Vbe -Vbe +Vbe = VBB2

So set INA to mid way between logic 1 and 0 and you can calculate VBB2.

For INB it's..

INB - Vbe + Vbe = VBB1

Basically the principle is that of a differential amp/long tailed pair configured as a comparator (eg one input fixed voltage).

http://en.wikipedia.org/wiki/Differential_amplifier
 

1. How does Emitter Coupled Logic work?

Emitter Coupled Logic (ECL) is a type of digital logic gate that uses transistors with a differential amplifier to process logic signals. It operates on the principle of current steering, where the output is determined by the difference in currents flowing through two transistors. This allows for high-speed and low-power operation.

2. What is the difference between NAND and AND gates in ECL?

In ECL, NAND and AND gates have the same basic structure, but they differ in the way they handle inputs. A NAND gate will produce a logical 0 output only when all of its inputs are logical 1, while an AND gate will produce a logical 1 output only when all of its inputs are logical 1. This means that the NAND gate has an inverted output compared to the AND gate.

3. How do you simulate a NAND gate in ECL?

To simulate a NAND gate in ECL, you will need two transistors with their emitters connected together. The inputs are connected to the base of each transistor, and the output is taken from the collector of the second transistor. When both inputs are logical 1, the output will be a logical 0. This can also be achieved by using a single transistor with its collector connected to the base, but this will result in a weaker output signal.

4. Can you explain the advantages of using ECL for logic gates?

ECL has several advantages over other types of logic gates. It operates at high speeds and consumes less power compared to other types of logic gates. It also has a wide operating temperature range and is resistant to noise and interference. Additionally, ECL can easily be integrated with other types of logic gates, making it a versatile choice for digital circuits.

5. Are there any limitations to simulating NAND/AND gates in ECL?

While ECL has many advantages, it also has some limitations. The circuit design for ECL gates is more complex compared to other types of logic gates, which can make it more expensive to implement. Additionally, ECL gates require a negative power supply, which can be a challenge in some applications. However, with advanced technology and design techniques, these limitations can be overcome, making ECL a popular choice for high-speed and low-power applications.

Similar threads

  • Other Physics Topics
Replies
3
Views
1K
  • Engineering and Comp Sci Homework Help
Replies
2
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
8
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
9
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
2
Views
4K
  • Engineering and Comp Sci Homework Help
Replies
1
Views
1K
  • Engineering and Comp Sci Homework Help
Replies
3
Views
1K
  • Engineering and Comp Sci Homework Help
Replies
2
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
10
Views
4K
  • Set Theory, Logic, Probability, Statistics
Replies
16
Views
1K
Back
Top