 Quote by schaefera
Hello, I'm trying to analyze the RC circuit... specifically a low-pass filter, so the set up is voltage source to resistor to capacitor, and the voltage source provides an oscillating voltage Vin, whereas I measure Vout across the capacitor.
I think I'm getting confused between two different possible analyses: first, comparing Vin and Vout and second, comparing the current and the voltage in the circuit. Please tell me where I'm going wrong.
If I consider the ratio Vout/Vin, I have the complex number: 1/(1+iwRC) which has the phase phi1= -arctan(wRC). This would imply that at very high w, the output voltage is 90 degrees behind the input voltage. But since at very high w the capacitor drops very little voltage, this circuit is essentially just a resistor dropping all the voltage. So why wouldn't we expect the output and input voltages to be IN phase in this case?
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The
current is (almost) in phase with V
in in this limit (ϕ
I = arctan(1/ωRC)). However, the voltage on the capacitor depends on how much charge it has. q = CV therefore dq/dt = i = Cdv/dt, where v is the capacitor voltage here. So what's happening is that, when V
in, and therefore the current, are at a maximum, the rate at which charge is accumulating on the plates is a maximum. So the capacitor voltage is only just ramping up to its maximum value. Hence the 90 degree phase lag. Once the capacitor voltage reaches a maximum value, dv/dt = 0, and hence i = 0, which is consistent with what is happening with the voltage source, which has already decreased in voltage down to 0, and is now going negative. Once it goes negative, the capacitor voltage is now greater than the source voltage, and the current reverses direction. The current i becomes large and negative, which means that the capacitor is discharging and its voltage is ramping down to its minimum (trailing the current in phase by 90 deg). Repeat this cycle over and over again.
 Quote by schaefera
Similarly, at very low w the capacitor drops most of the voltage and despite the fact that the phase angle approaches 0 in this limit. Since a purely capacitive circuit has a 90 degree phase shift, shouldn't we expect this shift to be present in that case?
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No, because here you have i = dv/dt = 0, and therefore V
out = V
in.
 Quote by schaefera
I think it would be easier if I could draw a phasor diagram, but I can only draw a phasor diagram to compare Vout (which would be the sum of capacitive voltage and resistive voltage, the two being at right angles to each other) to the current (which is parallel to the resistive voltage)... I wouldn't know where to place Vin on such a diagram would I?
Again, I think I'm getting confused between looking at Vout/Vin and Vout/Total current. Please tell me where my errors are! Thank you!
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I see no reason why you can't draw all three phasors on the same diagram.