Inter Logic Block Synchronization

[amonraa]

Hello,

I'm trying to design a simple digital circuit for learning purpose, and maybe later a bigger project.
The idea is to interface a microprocessor, probably a pure combinational logic block to do simple stuff, with a memory chip. Now what I need is a way to make sure that when I send an address on the address lines to memory, the processor should stop and wait until a stable output from memory is on the data buss so that it can process it. At the same time I need to do the same and wait for stable output from the processor before feeding it to next stages of the system. What techniques are available to achieve this kind of synchronization? I tried to Google the topic but could not come up with any useful information probably I was using the wrong terms anyway...

Your help is greatly appreciated.

 

[the_emi_guy]

The protocol for interfacing microprocessors to memories is constantly evolving. You will need to share with us which microprocessor you are using and which memory chip you would like to interface with.

 

[meBigGuy]

The simplist way is to "bit-bang" the memory. You set the address, assert the clock, and by then the data is probably valid and you can read it. If not, execute a no-op. Takes a lot of IO though and is very inefficient, data bandwith wise.

Beyond that requires intimate knowledge of the processor's IO system capabilities, and how much control logic you want to build and the performance you require. I'm wondering what useful function you might be aiming for.

A more useful project would be to interface to an external flash (SPI or TWI) and write the drivers to load/store data. SPI or TWI provides a useful interface to all sorts of interesting sensors and devices.

 

[amonraa]

The processor can be anything, something I designed a very simple combinational logic block, I'm just talking general not specific to any processor.

 

[the_emi_guy]

The simplist way is to "bit-bang" the memory. You set the address, assert the clock...

Asynchronous memories do not even have a clock.

OP need to tell us what devices he wants to use.

 

[amonraa]

Asynchronous memories do not even have a clock.

OP need to tell us what devices he wants to use.

I did not know it's device dependent, but I was thinking of a generic way to establish synchronization among different logic blocks, including memory.

 

[berkeman]

Memories are generally slaves to their processors, so the processor controls the timing. There is no synchronization per se. You just need to use a fast enough speed grade memory chip in order to keep up with the microprocessor. You look at the respective datasheets to figure out what speed grade memory chip you need to use.

If you are interested in learning about how to synchronize different logic blocks (that each have their own independent clock), that is a very interesting and real-world useful subject. See "Crossing Clock Domains" in this very good introductory paper by Peter Chambers (VLSI Technology Fellow):

"Ten Commandments of Excellent (digital) Design"

www.bawankule.com/verilogcenter/files/10_1.pdfEDIT -- BTW, you also use this synchronization technique when you have an asynchronous signal coming into a synchronous logic block (like a human pushbutton event coming into a clocked logic block). Quiz Question -- Why?

 

[meBigGuy]

LOL --- I tend to forget that asynchronous memories even exist.

I totally agree with everything you are saying. The Chambers paper you linked to had a lot of good stuff, but it didn't address data reconvergence very well.
Also, the most common clock crossing failures in modern fpga's are caused by skew variations in multibit values. That creates large (sometimes nanoseconds) windows that fail quickly (and can't be detected by functional simulations). metastability is an almost non-issue unless you are going very fast (where it is an extreme issue) or you are using a flop output as a clock.

I think the Chambers paper is a great place to start.

 

[meBigGuy]

The most common way to synchronize multiple logic blocks and a uP is via a bus. A processor bus is generally synchronous, and all asynchronous bus components deal with synchronizing to the uP bus. A bus generally supports data transfers and interrupts between bus components. Looking at BVCI or AMBA or Wishbone (at http://opencores.org/projects) would be a good way to get a handle on that.

The easiest way to play with all this is with an FPGA, some of which include a processor. The components at opencores.org are great examples, and are very usable.

 

[the_emi_guy]

I did not know it's device dependent, but I was thinking of a generic way to establish synchronization among different logic blocks, including memory.

It is absolutely device dependent.

BTW there are dozens of techniques for synchronizing logic blocks depending on the circumstances. This is a large part of what digital engineers do, decide which synchronization method to employ given the circumstances.

Just to give you an idea of the range of memory devices we deal with: a PCB that I am working with includes DDR3 memory and a one wire DS24B33Q memory.

The DDR3 is running so fast that we do not even bother to attempt to synchronize byte lanes. Its "flyby" topology leaves us with arbitrary, and potentially time varying, skew between the memory controller (in the processor) and memory devices. How can this possibly work? Both the memory controller and the memory device contain a mechanism where, cooperating, they measure the actual skew values. They then set programmable delays within the devices to compensate. This elaborate dance (called write leveling and read leveling) occurs periodically so that if the skew changes with temperature the compensation can track it.

On the other end of the spectrum, the DS24B33Q has only one wire (and ground). All communication with the part (and power as well), are delivered over this single wire. Interfacing with this part simply requires observing its particular protocol on that wire.

Between these two extremes there are many-many other memory interfacing schemes, probably hundreds if you include the obsolete ones.

 

[amonraa]

wow very interesting...and not as easy as I thought.

 

[the_emi_guy]

It can be easy, don't get discouraged. You just need to to some research, decide which memory device you are interested in experimenting with, and which processor you want to connect to.

We can help you fine tune/sanity check your decisions. For example you would not want to try to interface DDR3 DIMM to an Arduino.

 

[meBigGuy]

If you want to understand everything about interfacing, then you are facing a hopeless task. If you have some idea of what you want to do, or what you want to study, then it is pretty straightforward. Say you want to understand how an I2C interface to an eeprom works? Or an I2C interface to a sensor module or audio codec? (and it's only 2 wires). The task divides into two aspects. 1.) the I2C protocol, signal levels, etc and 2.) the command structure to the device you want to control.

You will always find at least those two elements. The signaling protocol, and the command structure. Each of those can have many levels depending on the interface, or be very simple.

So start with a better idea of what you want to do. You could grab an I2C eeprom data sheet and try to understand how it works.

 

[amonraa]

Basically I want to learn how to create my own mini-computer using FPGA as a simple processor and a memory which I'm not sure what would be the best in this situation. In other words, I want to create my own FPGA test board.

And now shall I ask another question which is a bit ambitious, but what type of oscillators (clock generator) they use in GHz computers? I looked up for GHz frequency crystal oscillator but could not find any. And what's the best square wave generator for implementing clock cycles at GHz frequency?

 

[the_emi_guy]

Basically I want to learn how to create my own mini-computer using FPGA as a simple processor and a memory which I'm not sure what would be the best in this situation. In other words, I want to create my own FPGA test board.

And now shall I ask another question which is a bit ambitious, but what type of oscillators (clock generator) they use in GHz computers? I looked up for GHz frequency crystal oscillator but could not find any. And what's the best square wave generator for implementing clock cycles at GHz frequency?

FPGAs these days contain memory internally. Do you have access to tools needed to program FPGAs and build PCBs?

The GHz signal that clocks your Pentium processor is generated within the Pentium chip. You will not be able to drive an external GHz rate clock into an FPGA.

amonraa, what is your background? Some of what you are attempting may be too ambitious.

 

[meBigGuy]

Go to opencores.com. You can find processors and other modules you can put inside an fpga. FPGA's have memory internally which you can learn how to use before you use external memory. All processors have internal memory, either cache or main memory. You need to start there. It seems like you are in way over your head.

 

[amonraa]

amonraa, what is your background? Some of what you are attempting may be too ambitious.

B.S Computer Engineering, but all my work experience is in software, so recently I decided to change directions and build hardware :)

I took one course in digital design but it's very elementary, and not much about all the details of what I want to do.

All digital design references are either very basic or very low level discussing the transistor layout and physics, so no practical information presented in those texts.

Ok I will reveal my project I'm trying to design:

A general computer system using FPGA and external memory, that runs at a speed comparable to current CPUs (I know too ambitious if even possible) but if I can make something fast enough to run Linux GUI that would be great.

 

[meBigGuy]

That is not physically possible. FPGA's are not capable of that sort of performance. I run a version of linux on a processor core in Xilinx Virtex 6 FPGA's. It is a 32 bit 5 stage pipelined processor with a single level cache. The FPGA cannot run much past 100Mhz. The 28nm FPGA technology cannot come close to even obsolete 180nm CMOS. This is because the internal FPGA routing delays of critical paths are 95% of the prop delay. (we use FPGA's to emulate our custom chip designs). Maybe you can double or triple that, but that won't give you the performance you need.

 

[meBigGuy]

I implement processors all the time (8 bit, 16 bit, 32 bit, custom DSP, custom controllers, etc) with and without external RAM (mostly without) and test them on FPGA's. There is no glory in doing that since many do it all the time. You can go get a core at opencores that will run linux, and another core to access external memory. I've mentioned opencores twice now. Have you bothered to look?