|Nov23-05, 11:17 AM||#1|
VHDL or Verilog if i'm a Computer Engineering Student?
Hello everyone, I'm a 2nd year computer engineering student, I was wondering if I should teach myself VHDL or Verilog? Some of my higher level CE friends said the school assumes you know VHDL programming, even though no other courses were taught on it. Do you recommend any good books/websites for VHDL or do you recommend learning Verilog? It seems like I would be able to learn Verilog alot easier because its syntax reminds me of C, as VHDL looks alot grosser. Thanks!
|Similar Threads for: VHDL or Verilog if i'm a Computer Engineering Student?|
|Computer Science vs. Computer Engineering||Academic Guidance||29|
|Engineering Student: Time Management||Academic Guidance||3|
|A not so genius engineering student||Academic Guidance||9|
|Engineering student minor?||Mechanical Engineering||4|
|Advanced Engineering Mathematics (For Computer Engineering)||Academic Guidance||4|