Register to reply 
Designing synchronous counter 
Share this thread: 
#1
May206, 05:56 PM

P: 19

Hey, I have some problems with my synchronous counter. Here is what I got. sorry for the big and bad quality of the pic. My scanner sucks :(
Here's the karnaugh map. I need to simplify them and use only NAND and inverters if needed. http://img101.imageshack.us/img101/7335/hw4na.jpg I need to design it in pspice (Schematics) along with the truth table. http://img101.imageshack.us/img101/1461/hw21sf.jpg Since the last two in the truth table is wrong, the whole thing is wrong. I know its probably some simple stuff but I can't figure it out. (2hrs now ) Thanks for anyone that can help. And if you want, I can upload the file for those who have pspice. Edit: I just found 2 errors in the Karnaugh map JB, but I'm pretty sure it doesn't change much. 


#2
May206, 05:59 PM

Mentor
P: 41,109

Ranger posted this link earlier today in the EE forum in response to a question on Synch Counters. Does it help?
http://www.allaboutcircuits.com/vol_4/chpt_11/3.html 


#3
May206, 06:12 PM

P: 19

I understand it. The thing is I can't find that wire (or gate) that is located wrong.



#4
May206, 06:21 PM

Mentor
P: 41,109

Designing synchronous counter
Second, I only see 8 Kmap drawings instead of 16 (oops, I mean F ). I see all 16 state transitions accounted for in your list, but not in the Kmaps. I could be missing your design strategy, though. Last, are the errors that you found already fixed in the Kmap that you posted the link to? I'll take a more detailed look if you think the linked Kmap is correct and sufficient. (EDIT  changed my dumb typo "AE" in 1st paragraph to "AF") 


#5
May206, 06:33 PM

P: 19




#6
May206, 07:33 PM

Mentor
P: 41,109

Okay, I think I see at least one error in the Kmaps (I get the 8map paradigm now, BTW). Look at JA term for square 4  it should be a 0, not a 1. For starting state 4, JK flop A has to hold a 0 to go to state 8. To hold a 0, JK = 0b0X, not the 0b1X that you show. Just work your way through all the Kmap squares carefully, and I think you'll get it right. I know it's a bit tedious...
Here's the map transition info that I used in my initial checks (just a reformatted version of what you have...how do I change the font to nonproportionally spaced courier or something...?) State(decimal, hex, binary), Next State(decimal, binary): 0 0 0000 1 0001 1 1 0001 2 0010 2 2 0010 4 0100 3 3 0011 1 0001 4 4 0100 8 1000 5 5 0101 1 0001 6 6 0110 1 0001 7 7 0111 1 0001 8 8 1000 9 1001 9 9 1001 1 0001 10 A 1010 1 0001 11 B 1011 1 0001 12 C 1100 1 0001 13 D 1101 1 0001 14 E 1110 1 0001 15 F 1111 1 0001 


#7
May206, 08:06 PM

P: 19

Thanks a lot. It really helped. I'm going to continue tomorrow because like you said, it is tedious. One mistake and the whole thing goes wrong.



#8
May206, 11:38 PM

P: 161

I did not go through the entire solution, but you made a mistake in the B flipflop (see schematics), where you have used JB = X1X0 + 00X1 when it should have been JB = 00X1.



#9
May306, 09:49 AM

Mentor
P: 41,109




#10
May306, 07:18 PM

P: 19

Good news. I started the whole thing over. I found another mistake on the kmart which added too extra NAND gates. I ran it and now it works out fine. Thanks for the help.



#11
Nov2510, 09:35 AM

P: 2

can any some one help me
Design a synchronous counter that goes through the sequence assigned to you. Any state that is not allowed should revert to the first state in the sequence at the first clock pulse. Use the 7476 and NAND only TTL. Use the following procedure: 1) Draw the state diagram. 2) Write the truth table. 3) Draw the excitation table for the JK flip flop. 4) Use Karnaugh Maps to simplify the logic control circuits for the flip flops. 5) Convert the logic control circuits for NAND only implementation. 6) Draw the synchronous counter using Circuit Maker and make sure it works. 7) Draw the synchronous counter using Schematics (PSpice). 8) Set up the clock for a 2 second period with 50% duty cycle. 9) Set up the simulation to run for 20 seconds. 10) Run the simulation. 11) Display the timing diagram showing the waveforms for the CLOCK, A, B, C, and D from the top down. 12) Print out the timing diagram. 13) On the schematic, change the information in the box in the lower right corner to reflect you, and print the page. 14) Write a paragraph describing how the circuit operates as it makes the transition between the third and the fourth state. ***** MUST USE SEQUENCE : 1234501 


#12
Nov2510, 02:49 PM

P: 2

hey hi i am goutam i have the same thing to do i have sequence 1234501 , can u help me to simplfy them and use only NAND and inverters if needed , i will post the picture i need to solve the karnaugh map
thanks................ plz reply 


Register to reply 
Related Discussions  
Designing a synchronous counter  Engineering, Comp Sci, & Technology Homework  4  
Trouble with 4 bit synchronous up counter  Electrical Engineering  12  
Design a synchronous counter that has a Moore output decimal  Engineering, Comp Sci, & Technology Homework  1  
Synchronous Counters  Engineering Systems & Design  0  
Designing a Synchronous Clocked State Machine.  Electrical Engineering  0 