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Conversion to NAND and NOR circuits

by Mo
Tags: circuits, conversion, nand
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Mo
#1
Jan19-07, 03:46 PM
P: 82
1. The problem statement, all variables and given/known data
Please see the attatched picture.


2. Relevant equations



3. The attempt at a solution

I can complete the first part of the question, but i am not sure how i should do the second part.

I would be grateful for a quick explanation or tutorial in how to do this part. I am aware of de Morgan's laws but cant seem to fully apply them to convert a whole circuit.

Im not looking for an explicit answer, im looking for a technique in how to solve the problem.

Thanks.
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berkeman
#2
Jan19-07, 04:11 PM
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Tell us what deMorgan's Laws are, and include an example or two.

Then please show us the solution that you got for the first part, and describe how you would implement it as written with NOT, AND and OR gates.

Then we can talk about how to use deMorgan's Laws to convert to the other form of the circuit....
Mo
#3
Jan19-07, 04:35 PM
P: 82
de Morgan's laws tell us how an AND can be converted to an OR.

Not (A.B.C) = NotA + NotB + NotC
Not (A+B+C) = NotA. NotB. NotC
e.g : Not A+B = NotA . NotB

For the first part i got:
CD + Not(A+B+C+D)

To get this i combined some of the expressions, then finally used demorgan's law as stated above.

and describe how you would implement it as written with NOT, AND and OR gates.


A + B = Not (Not A . Not B)
A . B = Not (Not A + Not B)

Umm not quite sure if this is correct, or if its what you want!

Thanks for your help so far.

berkeman
#4
Jan19-07, 05:01 PM
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Conversion to NAND and NOR circuits

I guess I was looking for the implementation in gates, for the final part of the problem.
Mo
#5
Jan19-07, 05:25 PM
P: 82
We would have 4 input A B C D.

We have a connection from both C and D to an AND gate (which is the CD part)

We also have a connection from all A B C D to a NOR gate. (which is the NOT A+B+C+D part)

Output from these two gates are then connected to an OR gate.
berkeman
#6
Jan19-07, 05:33 PM
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Remember, it said 2-input NAND and NOR gates, so you can't use a 4-input NOR for (A+B+C+D)
Mo
#7
Jan19-07, 06:12 PM
P: 82
In that case i think it would be possible to, applying de Morgan's laws, split up this 4 input NOR gate into two, 2 input NOR gates AND 'ed together.

NOT (A + B) . NOT (C + D)

The output of this would be equal to the 4 input NOR gate.

Regards.
berkeman
#8
Jan19-07, 06:16 PM
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That's pretty cool. I was thinking of the brute force way of using the 2-input NAND as an inverter (hook both inputs together), but your way is more creative and fewer gate delays.
Mo
#9
Jan19-07, 06:29 PM
P: 82
First of all, thanks for your help so far, secondly ... how would I go about tackling those next two parts of the question! It's mainly a case of getting the boolean expression into the correct form. (which im lost in!)

Regards,
Mo
berkeman
#10
Jan19-07, 06:36 PM
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Sorry, I have to bail from work now. I may be back online later tonight at home, but I'm not sure.

To try to help you more, I googled +minterm +maxterm +nand +nor, and got lots of good hits. Here's one that talks a lot about how to handle the two canonical logic forms (NAND and NOR), along with examples from K-maps to logic gate diagrams. Hope it helps:

http://www.vias.org/feee/karnaugh_09.html

Cheers.
Mo
#11
Jan19-07, 06:39 PM
P: 82
Thanks for the link and all your help. Good night.


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