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High Impedance in Verilog?

by l46kok
Tags: impedance, verilog
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l46kok
#1
Sep27-07, 07:56 PM
P: 296
1. The problem statement, all variables and given/known data

Provide the correct Verilog text for encoding the following numerical values:

A) A 16 bit hexadecimal with all positions in the high impedance state:

B) An unsized hex number BEEF

2. Relevant equations

Verilog Problem. There is no relavant equation to be used.

3. The attempt at a solution

What the.. I didn't even know a variable can literally be declared as high impedance. I thought high impedance state occurs when the variable is neither off or on.

Also, I thought the variables you declare in verilog MUST be sized.

How are these accomplished?
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#2
Sep29-07, 06:00 PM
P: 6
Quote Quote by l46kok View Post
1. The problem statement, all variables and given/known data

Provide the correct Verilog text for encoding the following numerical values:

A) A 16 bit hexadecimal with all positions in the high impedance state:

B) An unsized hex number BEEF

2. Relevant equations

Verilog Problem. There is no relavant equation to be used.

3. The attempt at a solution

What the.. I didn't even know a variable can literally be declared as high impedance. I thought high impedance state occurs when the variable is neither off or on.

Also, I thought the variables you declare in verilog MUST be sized.

How are these accomplished?
You actually can have the states as high-impedance. In your case, it would be

16'h????
or
16'hz

would work.

There is no such thing as unsized hex number. Even if you forget to declare the size, by default, verilog would size it as 32 bit.


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