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Verilog arithmetic shift implementation.

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l46kok
#1
Nov15-07, 07:24 PM
P: 296
Here's my verilog code first of all

module arithmetic_shift(input_num, op, shift_num, result);

input [7:0] input_num;
input [2:0] shift_num;
input op;
output reg [7:0] result;

always @ (*)

case(op)
0 : result = input_num <<< shift_num;
1 : result = input_num >>> shift_num;
default : $display("Error in Arithmetic Shift Module");
endcase
endmodule

module arithmetic_test;
reg [7:0] input_num;
reg op;
reg [2:0] shift_num;
wire [7:0] result;


arithmetic_shift UUT(input_num, op, shift_num, result);

initial
begin
input_num = 0;
op = 0;
shift_num = 1;

#50 input_num = 8'b10101010;
#100 input_num = 8'b11110000;
#150 op = 1;
input_num = 8'b11010001;
shift_num = 3;
end

endmodule

I am using Xilinx to run my simulation.

When I run the syntax check on my code, there are no problems at all. However, when I actually try to run the simulation, I get an error


# Loading work.arithmetic_test
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/verilog/xilinxcorelib_ver.arithmetic_shift
# Loading work.glbl
# ** Fatal: (vsim-3365) Testbench.v(12): Too many port connections. Expected 3, found 4.
# Time: 0 ps Iteration: 0 Instance: /arithmetic_test/UUT File: C:/Xilinx/verilog/src/XilinxCoreLib/XFFT1024_V1_1.v
# FATAL ERROR while loading design
# Error loading design



Stating that the instantiation being done on this particular line

arithmetic_shift UUT(input_num, op, shift_num, result);

Does not match the port connections with the actual module. Clearly, this cannot be true as there are 4 ports going in/out of the code.

So here's my question - did I write something wrong on the code to cause this trouble or is Xilinx smoking marijuana?
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