|Register to reply||
Propagation delay for carry lookahead adder
|Share this thread:|
Apr17-08, 07:55 PM
1. The problem statement, all variables and given/known data
1) I'm using a 4 bit carry lookahead adder to build a 8 bit parallel adder. I'm to calculate the maximum propagation delay time, assuming each gate introduces a unit time of propagation delay. I'm assuming not carry lookahead generators.
Would it just be 8 units of propagation delay?
2) If I had a 16 bit adder using carry lookahead generators, what would the maximum propagation delay time, assuming each gate introduces a unit time of propagation delay.
|Register to reply|
|Propagation Delay of Traces on PCBs||Electrical Engineering||13|
|How to use 4-bit parallel adders to perform 2Cs' subtraction?||Electrical Engineering||2|
|Create a byte-wide adder||Computing & Technology||5|
|Confused how do you calculate propagation delay of circuit and paths?||Engineering, Comp Sci, & Technology Homework||1|
|Full adder using decoder?||Electrical Engineering||1|