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Full Adder using a 3-to-8 Decoder in VHDL

by michael_mke
Tags: 3-to-8 decoder, full adder, vhdl
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Nov30-08, 09:54 PM
P: 5
I need to design a full adder using a 3-to-8 decoder.

I have the code for the 3-to-8 decoder but don't know how to use it as a full adder.
Please help. Thanks

//3-to-8 Decoder

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Decoder is
   port (
      A : in unsigned(2 downto 0);
      Y : out unsigned(7 downto 0));
end Decoder;

architecture Logic1 of Decoder is

   type TableType is array (0 to 7) of unsigned(7 downto 0);

   constant Table : TableType :=
      ( "00000001", "00000010", "00000100", "00001000",
        "00010000", "00100000", "01000000", "10000000");


   Y <= Table(to_integer(A));

end Logic1;
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