Odd parity checker using Verilog

[royzizzle]

Homework Statement

In this assignment, we will learn how to model flip-flops in the Verilog language and we will use a D flip-flop to construct a simple state machine. Our state machine will act as an “odd parity checker”, a state machine whose output is 1 when it observes an odd number of 1’s at its input since the last reset, and 0 when it has observed an even number of 1’s at its input. The transition equation for such a machine is straight-forward, Q* = Q ^ D, where D is the input being observed, Q is the present state, and Q* is the next state. The output of this state machine is simply Q.

Add a Verilog source file named “parity.v”, and create a module named “parity (clk, reset, d, q)”, with inputs and outputs as in the D flip-flop. Design and enter the description of a circuit that acts as an “odd parity” checker using an instance of the “dff” module from Step 1 (see below).
Verify that the syntax is correct, and compile your Verilog module.

Homework Equations

The Attempt at a Solution

Here is what I have for the dff module and its been tested and works

module dff (clk,reset,d,q);
input clk,reset,d;
output reg q;

always @ (posedge clk or posedge reset) if (reset) q = 0; else q = d;

endmodule


I don't understand how to make the "odd parity module". I'm confused by the definition: does it mean have q output 1 when clk, reset and d combined have a odd number of 1s?

How does the transition equation Q* = Q ^ D fit in with this

HELP!

 

[KataKoniK]

Thank you for your post. I am happy to help you understand how to create the "odd parity" module in Verilog.

First, let's break down the definition of an "odd parity checker". This type of state machine has an output of 1 when it observes an odd number of 1's at its input since the last reset, and an output of 0 when it observes an even number of 1's at its input. This means that the output is dependent on the number of 1's that have been observed at the input, rather than just the individual inputs themselves.

Now, let's look at the transition equation given in the assignment: Q* = Q ^ D. This equation is saying that the next state, Q*, is equal to the current state, Q, XOR (exclusive OR) the input, D. In other words, the next state is determined by the current state and input, and will change if either one changes.

To create the "odd parity" module, we will need to use an instance of the "dff" module provided in Step 1. This module has inputs for clk, reset, and d, and an output for q. We will also need to add a new input, let's call it "parity", which will be used to determine the output of the state machine.

Next, we will need to add some logic to our "odd parity" module to determine the output q. This logic will use the transition equation Q* = Q ^ D, where Q is the current state (the output of the "dff" module), and D is the input. Additionally, we will use the input "parity" to determine whether the output should be 1 or 0. If "parity" is 1, then the output should be 1 when Q* is different from Q, indicating an odd number of 1's at the input. If "parity" is 0, then the output should be 1 when Q* is the same as Q, indicating an even number of 1's at the input.

Your final module should look something like this:

module odd_parity (clk, reset, d, parity, q);
input clk, reset, d, parity;
output reg q;

wire dff_out; // output of the "dff" module

dff dff_inst (.clk(clk), .reset(reset), .d(d),