
#1
Apr2012, 07:08 PM

P: 78

Hi. I'm trying to build a quadrature sampling detector, or Tayloe detector based on the design at http://garageshoppe.com/wordpress/?p=371 . I intend to feed the I and Q signals into a ADC that uses a 1.65V reference. One thing I'm confused about is the purpose of the 2.5 VDC offset fed into the center tap of the transformer. It comes a voltage divider that halves the 5 V VDD, below is a circuit diagram I origionally assumed it's purpose is to provide an offset for an ADC but I'm not sure. The 47 nF capacitors are supposed to provide the "holding function" of the sample and hold action, but I'm not sure if the voltage on them will ever be 2.5V as the caps wouldn't have time to charge durring the sampling period. It also seems that the signal out of the 4 x bus switch would be a 2.5V pulse at the sampling frequency. Would the capaitors filter those out. According to my Bode plot for my corner frequency is about 3MHZ, and I'm trying to use a 5 Mhz sampling frequency. Am I looking at this all wrong? Thanks for the help in advance.
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#2
Apr2012, 08:33 PM

P: 1,784

Only if the sampling voltage is too noisy or sags too much during the sampling period would I increase the value. 


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