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Quadrature sampling detector circuit

by FrankJ777
Tags: quadrature sampling
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FrankJ777
#1
Apr20-12, 07:08 PM
P: 78
Hi. I'm trying to build a quadrature sampling detector, or Tayloe detector based on the design at http://garage-shoppe.com/wordpress/?p=371 . I intend to feed the I and Q signals into a ADC that uses a 1.65V reference. One thing I'm confused about is the purpose of the 2.5 VDC offset fed into the center tap of the transformer. It comes a voltage divider that halves the 5 V VDD, below is a circuit diagram I origionally assumed it's purpose is to provide an offset for an ADC but I'm not sure. The 47 nF capacitors are supposed to provide the "holding function" of the sample and hold action, but I'm not sure if the voltage on them will ever be 2.5V as the caps wouldn't have time to charge durring the sampling period. It also seems that the signal out of the 4 x bus switch would be a 2.5V pulse at the sampling frequency. Would the capaitors filter those out. According to my Bode plot for my corner frequency is about 3MHZ, and I'm trying to use a 5 Mhz sampling frequency. Am I looking at this all wrong? Thanks for the help in advance.
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skeptic2
#2
Apr20-12, 08:33 PM
P: 1,803
Quote Quote by FrankJ777 View Post
One thing I'm confused about is the purpose of the 2.5 VDC offset fed into the center tap of the transformer. It comes a voltage divider that halves the 5 V VDD, below is a circuit diagram I origionally assumed it's purpose is to provide an offset for an ADC but I'm not sure.
Look at your 4x bus switch. Its power supply is only 5V. That means it can only pass signals between 0V and 5V. In order to pass signals with the maximum peak to peak voltage, it needs to be biased to half the supply voltage

Quote Quote by FrankJ777 View Post
The 47 nF capacitors are supposed to provide the "holding function" of the sample and hold action, but I'm not sure if the voltage on them will ever be 2.5V as the caps wouldn't have time to charge durring the sampling period.
The I_Out and Q_Out lines should be very high impedance so the primary means of their discharge is back through the bus switch when it is closed. The capacitor may not completely charge during the sampling period but it will continue charging during the sample until it reaches 2.5V. If the bias plus signal is higher than 2.5V it will charge to more than 2.5V. When the signal plus bias is less than 2.5V the capacitor will discharge through the switch.

Quote Quote by FrankJ777 View Post
It also seems that the signal out of the 4 x bus switch would be a 2.5V pulse at the sampling frequency. Would the capaitors filter those out. According to my Bode plot for my corner frequency is about 3MHZ, and I'm trying to use a 5 Mhz sampling frequency. Am I looking at this all wrong? Thanks for the help in advance.
.
Yes the capacitors will filter out most of the sampling frequency. If you want to use a sampling frequency of 5 MHz, I would reduce the value of the capacitors to 10nF to start.
Only if the sampling voltage is too noisy or sags too much during the sampling period would I increase the value.


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