BCD 2-out-of-5 encoder

weeds

Can anyone please help with the design of a BCD 2 out of 5 encoder (74210 code) using basic logic gates

Ouabache

You have a very interesting digital project.

It is not clear from your question, what you have in mind.
Can you elaborate a bit on your project? Of course we are not here to do your homework, but certainly willing to steer you in the right direction.

What have you done so far on this? (are you familiar with basic logic gates, do you know what BCD and encoders are?)

weeds

Thanks for the reply:
I am familiar with Logic gates.I think the confusion is the BCD.I understand that a decimal number (0 to 9) is being represented by 1's and 0's.I am not sure how many inputs and outputs I should have and the mapping on a K-Map.See attchement for the truth table I must complete.This is the source of my misery.

I am required to design a BCD to 2-out-of-five- encoder.

DEC A B C D P7 P4 P2 P1 P0
0
1
2
3
4
5
6
7
8
9
ALL OTHERS 0 0 0 0 0 0 0

The above is supposed to be a truth table for the encoder (without boxes!)

Ouabache

Ok, on the BCD, yes decimal numbers are from 0 - 9, so what is the minimum number of bits you would need to represent 10 characters?

hint: 2 bits: 00, 01, 10, 11 ( or 2^2) could represent 0, 1, 2, 3
3 bits: 000, 001, 010, 011, 100, 101, 110, 111 ( or 2^3) could represent 0, 1, ... 7

In your description you mention 74210 code. Is that a coding scheme for BCD numbers?

To give you some ideas for your truth table, take a look at one on this spec sheet
---> http://www.datasheetarchive.com/data.../59/59104.html
this one happens to be for an 8-to-3 encoder.

weeds

Thanks for the reply.My input is a 4 bit number i.e 0001,0010,0011 etc till count ten.The 74210 code goes something like this,11000,00011,00101,00110,01001,01010,01100,10001,10010 and 10100(these correspond to P7,P4,P2,P1,P0).It has got two 1's for parity checking or error detection.I have done the kMaps (any hints on kmaps) and drew the circuits.I am left with building the circuit using micro cap and testing.I would welcome ant hints.Thanks

pervect

If you've done the maps, you should have a Boolean logic expression that represents your truth table - or haven't you gotten that far?

Ouabache

Okay i follow you now.. The ABCD is a 4 bit binary-coded-decimal, and your P7,P4,P2,P1,P0 is the 5 bit (74210 code)

(74210 code) is also known as the POSTNET Barcode
see ---> http://www.kuro5hin.org/story/2002/4/12/21757/8647

You mention: ALL OTHERS 0 0 0 0 0 0 0
Do you mean: your design criteria specifies that input values 1010 thru 1111 all have output values of 0 0 0 0 0? Or do you have flexibility to choose them as "don't care" conditions (X)? (if so, that would certainly simplify your logic)

Are you also incorporating the parity check into your digital logic??

I see plecompte is designing the same encoder and looking for clues on another forum. Perhaps you are following that too.. ----> http://forum.allaboutcircuits.com/in...showtopic=1614

Ouabache

If you created Kmaps (without using don't care conditions for inputs 1010 thru 1111) what logic expressions did you get for P0, P1, P2, P4, & P7?

I also made Kmaps & obtained expressions for your 5 outputs (without using don't care conditions) and can give you feedback?

weeds

Ouabache!!Thanks so much for the help.I have never researched anything the way I did about this particular assignment.Thanks for not telling me the answer.I managed to get the 5 output equations for P0 through to P7 using KMaps.Using micro cap I drew the circuit (logic) fed my inputs A,B,C and D and what I got as outputs (P7...) matched my Truth table.
I might have a few more gates than required but I am definately onto it.I did not use don't cares .

And Pervect can you tell me more about "ab caNeffg DehNiD jN kal " it's a new one.

Thanks Guys

Ouabache

You're welcome.. I think we are all here to learn something and if we help some folks along the way, that's a bonus..

ALJ

Ouabache,
What were the expressions that you produced from your Kmaps. I am also struggling with the same problem as weeds.

I have produced the truth table but am having a bit of difficulty with the Kmpas and logic diagrams for the BCD to 74210 encoder.

Any assistance would be appreciated.

ALJ

Ouabache

It would be better, if you can show the expressions you have figured out so far, and I'll try to show you where you are going astray.
(that will also give me a chance to go dig up where i put my scratch paper for that problem... you're lucky i didn't throw that one away)

Kenneth Mann

The difficulty seems to have less to do with the problem itself than with working with Karnaugh Maps. Maybe one of us should give an introductory tutorial in using these (we would assume that basic logic is understood). I could do so (estimate four or five or so sections), if there is interest in it. The problems I see are two. First, the space allowed in this forum is only about 25K bytes for an attached file, and the maps I have take about 30 to 90K. Second, by the time it is done it would likely be too late for ALJ's assignment. In any case, if anyone knows how to input larger attachments, and if anyone is interested, I can show how "Reflective Karnaugh Maps work.

KM

Ouabache

Ken, perhaps you are right. Maybe you could post a K-map for one of the outputs as an example. It sounds like there would be space for one.

MirrorM

Hi

Im having trouble drawing the circuit in micro cap. Would someone please happy me with this or drop a few hints. Would it be correct in saying that I have to have 2 leds turn on for each of the outputs?

Ive also been told that this circuit can be build with 8 or 9 ics only, do you believe this to be correct.

Thanks

weeds

[QUOTE=Ouabache]It would be better, if you can show the expressions you have figured out so far, and I'll try to show you where you are going astray.
(that will also give me a chance to go dig up where i put my scratch paper for that problem... you're lucky i didn't throw that away)

this is what I got for my output.can this be simplified any further.No use of exclusive gates.Do not tell the answer just hints

Thanks

P0=A'BC'D'+A'B'C'D+A'BCD+A'B'CD'

P1=AB'C'D'+A'B'D+A'C'D

P2=AB'C'D+A'B'C+A'CD'

P4=A'C'D'+A'BC'+A'BD'

P7=A'BCD+B'C'D'+AB'C'

Ouabache

I can't help with the first one, I don't have micro cap. You might ask weeds, I think he is familiar with that program.

Whether you can build this with 8 or 9 ICs, it depends on which ICs are available to you. For example some ICs have 4 gates/chip with 2 inputs/gate. Some have 3 gates/chip with 3 inputs/gate, and yet another has 2 gates/chip with 4 inputs/gate. You're lucky you haven't been told you can only use one type of gate (for example NAND). That was a spec I had to work with one time.