Delay through CMOS Inverter.

by klen
Tags: digital circuits, digital electronics, logic gates, propagation delay
klen is offline
Jul30-13, 05:54 AM
P: 10
When calculating delay, like the fall time delay of the output, through an inverter with rc model of the transistors (assuming Cmos inverter) why do we neglect the short circuit current through the device and what are the assumptions.

Can anyone explain this?
Phys.Org News Partner Engineering news on
Lifting the brakes on fuel efficiency
PsiKick's batteryless sensors poised for coming 'Internet of things'
Researcher launches successful tech start-up to help the blind
Baluncore is online now
Aug1-13, 03:12 AM
P: 1,282
By short circuit current I assume you are referring to the short period while both the upper and lower output drivers may be conducting at the same time. If it occurs, that short duration current is limited by the inductance and resistance of the path.

Any short circuit current is flowing through a potential divider comprising one complementary transistor pair. The signal is propagating perpendicular to the short circuit current and so is not effected. Any minor influence on the simple model will be taken into account by adjustment of the RC parameters.

Register to reply

Related Discussions
CMOS inverter DC analysis Electrical Engineering 2
CMOS inverter circuit, spike in simulation Engineering, Comp Sci, & Technology Homework 2
interview Q - CMOS inverter Engineering, Comp Sci, & Technology Homework 3
cMOS inverter circuit question Engineering, Comp Sci, & Technology Homework 1
CMOS inverter Engineering, Comp Sci, & Technology Homework 0