# 2:4 decoder solution confusion

1. Apr 27, 2014

### anhnha

Hi.
I am confused a bit about the solution for 2:4 decoder in the picture below.
Thanks.

#### Attached Files:

• ###### 2-4 decoder.jpg
File size:
24.6 KB
Views:
113
2. Apr 27, 2014

### Mordred

Think of the binary equivalent, 2 bits has how many possible conditions? The circuit is a translation of the Boolean logic. work out your boolean truth table. of a 2 bit circuit, then draw the same circuit with and or gates.

3. Apr 27, 2014

### anhnha

Hi.
I understand all possible conditions. I didn't draw Y1, Y2, Y3 because they are same in terms of implementation.
My confusion about Y0.
I am wondering why the author used that solution not mine.

4. Apr 27, 2014

### Mordred

most likely ease of understanding the address bus relation. Notice that he's taken care to add both conditions of A0 and A1 in seperate lines where you did an equivalent with use of strictly high inputs? In the first case its easier for someone new to understand. Its easier to correlate the truth table to desired conditions.

edit: hes mapped the addressing in the following sequence for visual ease.

00
01
10
11

You've mapped
11 with an inverted condition later on then
01
10
11 or at least I hope you did as you only showed one decoded gate

Last edited: Apr 27, 2014
5. Apr 27, 2014

### anhnha

Thanks. I see no difference in functioning between my solution and the key in the book.
I also can derive the circuit given in the solution.
However, I can't figure out why the author used the key solution not the one I get above.

6. Apr 27, 2014

### mjhilger

I would say that the book design is such to keep the loading on inverted and non-inverted signals equal. Also if you look at the book solution, the output is virtually identical for each pin. This could also be to keep the propagation times equal in all outputs. There are numerous ways to solve a problem, but sometimes you need to see the complete solution and keep things in sync and balanced as possible for other reasons.

Your output stage using 2 transistors to pull the signal to rail, will cause a different voltage output when a current is supplied on a "high" output. This results in different output characteristics for different pins, again not a good thing. You really want the outputs and prop times equal for the outputs.

Last edited: Apr 27, 2014