3-input AND - NAND equivalent?

  • Thread starter rjs123
  • Start date
  • Tags
    Equivalent
In summary, the conversation discusses the conversion of a 3-input AND gate to NAND gates, with the goal of using as few NAND gates as possible. The final expression to be converted is ga + za + sgz, and it is shown that it can be done with only six 2-input NAND gates. The conversation also includes another expression for practice, which is condensed to b~ce(a + d) + c(de + ab + ad~e), and the final solution is c(de + da + ab) + b(ae + de). A circuit diagram is provided for the solution.
  • #1
rjs123
90
0

Homework Statement



I'm trying to convert the 3-input AND gate shown below using only NAND gates...but am having troubles. Is it possible to use only 2 NANDS for the conversion?


http://www.doctronics.co.uk/images/4081_03.gif [Broken]
 
Last edited by a moderator:
Physics news on Phys.org
  • #2
What about a 3 input NAND followed by a two input NAND used as an inverter?
 
  • #3
I'm trying to convert this expression: ga + za + sgz

using just 2-input nand gates...more specifically the 7400 ic chip.

I'm trying to use as little NAND gates as possible. I've got (ga + za) down to 5 NAND gates currently...I can only use 8 total NANDS for this.
 
  • #4
rjs123 said:
I'm trying to convert this expression: ga + za + sgz

using just 2-input nand gates...more specifically the 7400 ic chip.

I'm trying to use as little NAND gates as possible. I've got (ga + za) down to 5 NAND gates currently...I can only use 8 total NANDS for this.

I can do that expression with six 2-input NANDs. I don't see how to show you how without showing the solution. Is this a homework problem to hand in?
 
  • #5
LCKurtz said:
I can do that expression with six 2-input NANDs. I don't see how to show you how without showing the solution. Is this a homework problem to hand in?

Here is what I got...this is a practice problem to prepare for a midterm, but I would like to see how you used 6 NAND gates.

http://img827.imageshack.us/img827/7766/schematic.jpg [Broken]
 
Last edited by a moderator:
  • #6
rjs123 said:
Here is what I got...this is a practice problem to prepare for a midterm, but I would like to see how you used 6 NAND gates.

OK. Here's my circuit. One NAND is used as an inverter.

forumcircuit.jpg
 
  • #7
LCKurtz said:
OK. Here's my circuit. One NAND is used as an inverter.

forumcircuit.jpg

thank you. I have one more expression for practice problems:

ab~ce + b~cde + cde + abc + acd~e (The ~ symbol represent "not")

I'm supposed to do this expression in 12 gates.

I currently have the last 3 condensed to: c(de + ab + ad~e)

The first two: b~ce(a + d)

so the final condensed form looks like this: b~ce(a + d) + c(de + ab + ad~e)

if you can try helping me convert this expression into a NAND diagram that would be great...thanks for your help again.
 
Last edited:
  • #8
You have written ab&ce

Is this any different from a&b&c&e ?
 
  • #9
NascentOxygen said:
You have written ab&ce

Is this any different from a&b&c&e ?

I changed the above post...it should be tilde symbols ~ for "not".
 
  • #10
But in the expression ab~cd is it the b or the c that is the not? You can make the expressions much more readable with tex, like this: ##ab\bar cd##. Here's how you enter it:
Code:
##ab \bar cd##
 
  • #11
rjs123 said:
I currently have the last 3 condensed to: c(de + ab + ad~e)
Consider de + ad¬e
Take out the term d,
d (e + a¬e)

when e is TRUE, the bracketed expression = e
when e is FALSE, the bracketed expression evaluates = a

So,
d (e + a¬e) = d (e + a) = de + da

So c(de + ab + ad~e) = c (de + ab + ad) = c( d(e+a) + ab)

In the absence of better advice, I would implement paired terms, e.g.,
I would form E+A
then AND it with D
then form AB
then OR these two terms (using NAND gates)
then AND with C
then ...

This seems rather pedestrian, hopefully someone else has a better idea. :smile:
 
  • #12
duplicate
 
Last edited:
  • #13
original form: ##ab \bar ce## + ##b \bar cde## + ##cde## + ##abc## + ##acd \bar e##

condensed form: ##b \bar c(ae + de)## + ##c(de + ab + ad \bar e)##

partial circuit diagram using NANDS ##c(de + ab + ad \bar e)##:

I made that portion with 7 NANDS...I still have to finish the ##b \bar c(ae + de)## portion of the diagram...still have 5 NANDS left.

hjkh.jpg
 
  • #14
i figured it out thanks to oxygen's logic...I checked all 32 combinations for all the letters related to the problem...and all of the outputs came out correct.

final condensed form: c(de + da + ab) + b(ae + de)

heres my diagram:

tit.jpg
 
Last edited:
  • #15
rjs123 said:
i figured it out
Good.

http://s16.postimage.org/mb1ot390j/tit.jpg

final condensed form: c(de + da + ab) + b(ae + de)
I think you unnecessarily duplicated D NAND E
when you could have used the output twice?
 
Last edited:

1. What is a 3-input AND - NAND equivalent?

A 3-input AND - NAND equivalent is a logic gate that accepts three binary inputs and produces a single output. It is equivalent to a combination of AND and NAND gates, where the output of the 3-input AND gate is fed into the input of a NAND gate. This results in a NAND gate with three inputs, producing the same output as the 3-input AND gate.

2. How does a 3-input AND - NAND equivalent work?

A 3-input AND - NAND equivalent works by implementing the logical operation of AND followed by NOT (or NAND). This means that the output will only be true (1) if all three inputs are true, otherwise the output will be false (0). This logic can be represented using a truth table, where all possible combinations of inputs and their corresponding outputs are shown.

3. What is the difference between a 3-input AND - NAND equivalent and a regular 3-input NAND gate?

The main difference between a 3-input AND - NAND equivalent and a regular 3-input NAND gate is that the former combines the functions of an AND gate and a NAND gate, while the latter only performs the NAND operation. This means that the output of a 3-input AND - NAND equivalent will be the same as a regular 3-input NAND gate, but with an additional AND operation included in its functionality.

4. What are the practical applications of a 3-input AND - NAND equivalent?

A 3-input AND - NAND equivalent can be used in various electronic circuits and systems, such as in digital logic design and microprocessors. It is also commonly used in computer memory and data storage systems, where it helps to control the flow of data and ensure accurate processing. Additionally, it can be used in control systems for industrial automation, as well as in communication systems for signal processing and error detection.

5. Can a 3-input AND - NAND equivalent be used as a replacement for an AND gate or a NAND gate?

Yes, a 3-input AND - NAND equivalent can be used as a replacement for an AND gate or a NAND gate, as its functionality is equivalent to a combination of the two. However, it may not always be the most efficient or cost-effective option, depending on the specific application and requirements. It is important to consider the specific needs of the circuit or system before deciding on the appropriate gate to use.

Similar threads

  • Engineering and Comp Sci Homework Help
Replies
8
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
1
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
2
Views
4K
  • Engineering and Comp Sci Homework Help
Replies
3
Views
1K
  • Engineering and Comp Sci Homework Help
Replies
1
Views
6K
  • Engineering and Comp Sci Homework Help
Replies
4
Views
26K
  • Engineering and Comp Sci Homework Help
Replies
9
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
10
Views
2K
  • Engineering and Comp Sci Homework Help
Replies
10
Views
3K
  • Engineering and Comp Sci Homework Help
Replies
10
Views
4K
Back
Top