# 5 to 24 decoder from 3 to 8 decoders

• spingk
In summary, the conversation discusses the design of a 5:24 decoder using three 3:8 decoders and one 2:4 decoder. The first step is to create a truth table with 33 lines, starting with EN X:43210 and Y: and filling in the corresponding values for each line. The solution then moves on to drawing a block diagram of the final decoder, with X4 as the MSB and X0 as the LSB. The individual decoders need to be properly connected to create the desired decoder, which may require using gates. Further guidance is requested for drawing the block diagram.
spingk

## Homework Statement

Design a 5:24 decoder using three 3:8 decoders and one 2:4 decoder.
1)Show the truth table.
2)Draw a block diagram of the final decoder. Use X4 as the MSB and X0 as the LSB.

2. The attempt at a solution
I have the truth table drawn. Because it is a 33 line truth table I don't want to type it out. But I start out with:
EN X:43210 Y:
0 xxxxx
1 00000 Y0=1
1 00001 Y1=1
...
1 10111 Y23=1

I am having trouble figuring out how to connect the decoders to get a proper decoder.

Last edited:
In the past we have drawn out the circuit diagrams with gates, but this seems to be slightly different. Could I get some help on how to draw the block diagram?

I would first start by reviewing the basics of decoders and their functions. A decoder is a digital circuit that converts coded inputs into coded outputs according to a specified logic function. It essentially takes a binary input and activates a specific output line based on the input code.

In this case, we are asked to design a 5:24 decoder using three 3:8 decoders and one 2:4 decoder. This means we need to take a 5-bit binary input and produce a 24-bit output. This can be achieved by using three 3:8 decoders, each with 3 input lines and 8 output lines, and one 2:4 decoder with 2 input lines and 4 output lines.

To start, we can label the three 3:8 decoders as A, B, and C, and the 2:4 decoder as D. The inputs to the decoder will be labelled as X4, X3, X2, X1, and X0, with X4 being the most significant bit (MSB) and X0 being the least significant bit (LSB). The outputs of the decoder will be labelled as Y23, Y22, Y21, ..., Y1, Y0, with Y23 being the most significant bit (MSB) and Y0 being the least significant bit (LSB).

To create the truth table, we need to consider all possible input combinations for the 5-bit binary code. This means we will have 32 rows in our truth table, with each row representing a different input combination. The outputs for each row can be determined by the following logic function:

Y23 = A0 * B0 * C0 * D0
Y22 = A0 * B0 * C0 * D1
Y21 = A0 * B0 * C1 * D0
Y20 = A0 * B0 * C1 * D1
Y19 = A0 * B1 * C0 * D0
Y18 = A0 * B1 * C0 * D1
Y17 = A0 * B1 * C1 * D0
Y16 = A0 * B1 * C1 * D1
Y15 = A1 * B0 * C0 * D0
Y14 = A1 * B0 * C0 * D1
Y13 = A1 * B0 *

## 1. What is a 5 to 24 decoder from 3 to 8 decoders?

A 5 to 24 decoder from 3 to 8 decoders is a digital logic circuit that takes in 5 input signals and generates 24 output signals based on the input combinations. It is constructed using three 3 to 8 decoders and additional logic gates.

## 2. How does a 5 to 24 decoder from 3 to 8 decoders work?

The 3 to 8 decoders in the circuit decode the first three input signals and generate 8 possible combinations. These combinations are then used as inputs for the third 3 to 8 decoder, along with the remaining two input signals. The output of this third decoder is then combined with the outputs of the first two decoders using additional logic gates to generate the final 24 output signals.

## 3. What is the purpose of using a 5 to 24 decoder from 3 to 8 decoders?

The purpose of using this decoder is to expand the number of input and output possibilities for a circuit. It is commonly used in computer memory systems, address decoders, and other digital systems where a large number of inputs and outputs are required.

## 4. Can a 5 to 24 decoder from 3 to 8 decoders be used in reverse?

Yes, a 5 to 24 decoder from 3 to 8 decoders can also be used in reverse. This means that it can take in 24 input signals and generate 5 output signals based on the input combinations. However, in this case, the circuit would require additional logic gates to reverse the decoding process.

## 5. What are the limitations of a 5 to 24 decoder from 3 to 8 decoders?

The main limitation of this decoder is that it can only decode up to 5 input signals into 24 output signals. If more input signals are required, then multiple decoders would need to be cascaded, which can lead to increased complexity and delay in the circuit. Additionally, the circuit may also consume more power due to the use of additional logic gates.

• Engineering and Comp Sci Homework Help
Replies
1
Views
8K
• Engineering and Comp Sci Homework Help
Replies
18
Views
6K
• Engineering and Comp Sci Homework Help
Replies
2
Views
9K
• Engineering and Comp Sci Homework Help
Replies
1
Views
5K
• Engineering and Comp Sci Homework Help
Replies
4
Views
2K
• Engineering and Comp Sci Homework Help
Replies
5
Views
2K
• Engineering and Comp Sci Homework Help
Replies
4
Views
2K
• Engineering and Comp Sci Homework Help
Replies
1
Views
2K
• Electrical Engineering
Replies
10
Views
3K
• Engineering and Comp Sci Homework Help
Replies
15
Views
2K