# And gate

The AND gate 1. When A = 0 and B = 0 both diode D1 and D2 get forward biased and hence conduct. The diodes being ideal, no voltage drop takes place across either diode. Therefore potential difference of 5V takes place across R, with C at zero potential with respect to earth. Thus the output Y is 0 (in level).
2. When A = 0, B = 1, D1 conducts diode D2 will not. Since D1 is ideal, no voltage drop occurs it. Therefore a voltage drop of 5V takes place across R, having D at +5V and C at zero with respect to earth. The output is 0 (in levels).
3. When A = 1, B = 0 for same reason, output is 0.
4.When A = 1, B = 1 none of diodes conduct and so no current flows through R. The potential at C is equal to potential at D which is +5V with respect to earth. Hence output Y is 1.

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

K^2
Ingenious invention. I wonder why nobody ever thought of doing anything like that before. To think, if we put enough of these together, we can make arbitrary computations with these things. We can even construct a telecommunications network where people are free to exchange ideas like that with each other.

Before CMOS (complemenatry metal oxide semiconductor), there was TTL (transistor transistor logic), DTL (diode transistor logic), RTL (resistor transistor logic), and DL (diode logic). The fundamental flaw in DL logic was that it could not perform the NOT logic operation, like in NAND. Two cross-coupled NAND gates are a simple flip flop.

Bob S

I ate cornflakes for breakfast.

What's the point of OP?

The diode AND gate above lacks two of the fundamental requirements of multistage logic. To complete the set, an inverting element is required. This cannot be done with diodes and resistors alone as Bob has noted. Second, diode AND gates cannot be cascaded indefinitely before the high logic level (in this case) degrades. Signal degradation correction is a global requirement as true for digital logic as it is for digital or analog neuronetworks.

4.When A = 1, B = 1 none of diodes conduct and so no current flows through R. The potential at C is equal to potential at D which is +5V with respect to earth. Hence output Y is 1.

How?

My mistake. Not the high level but the low level signal degrades over multiple stages in your design. For an input of zero volts on either input the output is a diode drop above ground. Successively it goes to two, three, and more diode drops until it reaches the logic high level.

Do you think you can come up with a gate using a transistor?

vk6kro