Apparent violation of KVL

[caesius]

Homework Statement

Not really a problem, but we're learning about source-free RL circuits and the instructor was deriving the current w.r.t time. I've actually seen this derived a few times but one thing has always bothered me.

Looking at this picture recreated from the text

http://homebrew.net.nz/RL.png [Broken]

The equation dervied from it says:

Ri + vL = 0

which implies vR + vL = 0

but I've always thought that with KVL you simply write down the first sign you hit when tranversing the circuit, i.e., why is the equation not

-vR + vL = 0

Surely since the two components are in parallel the voltage drop across them has to be equal??!

Thanks if anyone can clear up my confusion

 

[davieddy]

Surely since the two components are in parallel the voltage drop across them has to be equal??!

They are in series. We want to say that the currents through
L and R are equal. We use this circulating current direction as
our sign convention for vL and vR.
vL +vR = 0

 

[Redbelly98]

Since the direction of i is defined opposite to the actual current you'd get with a positive voltage across R, we have

V_R = - i R​

Equate this expression with V_L and see what you get.

p.s. FYI, in this case the two elements are both in parallel (same voltage) and in series (same current).