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ASK Demodulator

  1. Jun 26, 2013 #1

    I am designing an ASK demodulator for RFID Tags. I have attached the circuit diagram. This is the ckt from IEEE paper.
    If you look at the ckt, the first stage is the inverter kind of thing. I didn't get why second NMOS is used for Stage I. Similarly, the second stage is also inverter with two NMOS. Again, the question is why second NMOS. But when I checked the output of that stage, it is acting like a latch. The last stage is buffer.

    I generated ASK modulated signal and fed as input to the demodulator. I expected that whenever modulated signal is present, demod output is '1' and when no signal is present, it is '0'. To my great surprise, it is always '1'. I tried to give the input by delaying it. So, for the very first time, because of the delay, I could see a logic '0`' at the output. After the delay, there is signal and so the output is logic '1'. Afterwards, though there is no signal, I don't see logic 0 at the output. Its always high. I assumed that the second NMOS at second stage is acting like a latch. Please let me know how can I redesign it? Or Is my understanding wrong? I have attached the simulated results.

    Attached Files:

  2. jcsd
  3. Jun 26, 2013 #2
    Is the circuit you attached the one you built? The gates of the last inverter are floating. if you built your circuit that way it isn't going to work.

    The circuit works like this:

    In the first stage, the second nmos is in series with the first so it is equivalent to making the first nmos wider. Therefore it pulls down harder. I assume the inverter was drawn that way to indicate that the inverter threshold is higher than mid-scale.

    In the second stage, the second nmos is a current source, presumably there to bias the second inverter into its high-gain region. (the gain of an inverter in submicron CMOS is on the order of 10). The part labeled "3" looks like it should be a very simple comparator, although like I said in the previous paragraph it isn't hooked up correction (the gates are floating in the second inverter0.

    Did that help?
  4. Jun 26, 2013 #3
    Part '3'....I have connected the drains to the gates. I believe the connection is missing in the figure. Yaa, what u said about the operation of ckt is right. But I don't understand whenever signal is there, output should be logic '1' and when no signal present, logic '0' should be at output. I don't see such behavior here. Once the ckt provides logic '1', the output stays on logic '1' though there is no signal at the input. What should be the work around on this ckt, if I want to see my expected output?

    I have uploaded the circuit I have simulated and its results. I have used M2 and M11 to generate ASK modulated signal. The other part is the demodulator circuit which I have uploaded as the first post. Coming to the results, Simulation.png shows the voltage on the nets - "in", "mm_out", "sig_out" and "output". In this plot, I expected that whenever "mm_out" is high, "sig_out" should be low. But this behaviour is never happening. The final plot is Vgs and Vth of M7, M3 and M12.

    Attached Files:

    Last edited: Jun 27, 2013
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