Designing Asynchronous Up-Down Counter w/ SN 7474

[munkachunka]

Hi there, I am working my way through some past exam papers and am stuck on this question, the answer that was given to me with the past exam was wrong so I have no reference, I cannot find anywhere on the net or in books the type of cct I am trying to design.

In previous parts of the question I have drawn the cct diagrams for an Up-counter and a down counter using 3 SN 7474 D type flip-flops. The only difference between the ccts being where the feedback is taken from, I.e Q or Not Q.

The question is "there is a requirement to either clear all Q outputs or present them to 1 witht the input clock to the first stage (flipflop A) stopped. Include suitable switches and Logic dates, draw the diagram for the complete Up-down counter.

I think I need to attach the IP/s of Set and Reset to a switch which would either set or reset the switch when the OP goes low, this would be done using a not gate to reset.

I am not sure how to integrate the up and down counters together, The only counters that I can find similar to this use J/K's.

Any help would be appreciated.

 

[Jonno]

If you have a switch that provides a logic '0' to change the counter from up to down then try come up with the boolean expression for the clock inputs Bistables B and C.

The clock inputs of the Bistable B is driven by the ouput of Bistbale A. Q to up count and not Q to down count. What you need is a few gates in between the Q and not Q outputs and the D input of the next Bistable.

Hope that makes sense but having just spent an hour or so on this very problem I'm hesitnent to give the answer straight to you.

See you in March (maybe)

 

[piercas]

Hello,

Thank you for reaching out for help with your design problem. I understand the importance of accuracy and precision in designing circuits.

Based on your description, it seems like you are trying to design an asynchronous up-down counter using SN 7474 flip-flops. In order to achieve the desired functionality, you will need to incorporate additional logic gates and switches into your design.

First, let's take a look at the requirement to clear all Q outputs or present them to 1 when the input clock to the first stage is stopped. This can be achieved by connecting the Set and Reset inputs of all flip-flops to a switch that can toggle between the two states. When the switch is in one state, it will set all outputs to 1 and when it is in the other state, it will clear all outputs to 0. The switch can be controlled by a logic gate that detects when the input clock is stopped.

Next, to integrate the up and down counters, you can use a multiplexer (MUX) that selects the input based on the direction (up or down) of the counter. This MUX can be controlled by a switch or a logic gate that detects the direction of the counter.

I understand that you may have only seen J/K flip-flops being used in similar counters, but the same functionality can be achieved using D flip-flops with additional logic gates. If you are still unsure about how to integrate the up and down counters, I suggest consulting your textbook or an online resource for guidance.

I hope this helps you in designing your asynchronous up-down counter. Best of luck with your exams!