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Behaviour of CMOS transistors

  1. May 4, 2010 #1
    Full Disclosure: This is coursework

    I study Electronics and Software Engineering, but due to my university not exactly having the best planning skills, I've been thrown into a piece of Third year Microelectronics coursework when I have never taken a MicroElectronics module in my career.

    Basically, I'm looking for recommendations on resources (or really good explanations) of the characteristics and behaviour of p-channel load and n-channel load CMOS transistors upon variations in substrate length and width, and the interaction of these values in Op-Amp design (ie current mirror + differential amplifier).

    I understand the behaviour from an electrical perspective but can't quite get my head around the impacts in behaviour upon changing these variables, and would greatly appreciate some help and guidance.

    Cheers
     
  2. jcsd
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