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Homework Statement
The question is shown in the picture attached. I have also attached my attempt of the circuit using logic gates.
The Attempt at a Solution
This is my answer:
A’.B.C’.D’ + A’.B.C.D + A.B’.C’.D’ + A.B’.C’.D + A.B’.C.D’ + A.B.C.D’
= B.A’(C’.D’+C.D) + A.C.D’ + B’.A.C’
=B.A’.(C⊕D)' + A.C.D’ + B’.A.C’
Have I made any errors and does this look like the most effective way of drawing this circuit using 'standard' logic gates?
Thanks :)
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