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Broadbanding a CE

  1. Jul 7, 2006 #1
    I have a project to build a discrete operational amplifier with 1000 gain with a bandwidth from DC to 12 Mhz. I am trying to have one gain stage that sets the dominant pole at 12 Mhz and the other stages have poles at 100 Mhz while trying to keep the number of gain stages to a minimum for simplicity's sake.

    Someone suggested for me to try a simple common emitter with emitter resistance. By adjusting the Re so that the zero coincide with the 1st pole, I can eliminate it and basically extends the bandwidth to its second pole.

    I am having trouble finding the high frequency equation for this circuit though. All the materials I have looked at solving the high frequency without Re using the pi model. It seems placing the Re in there complicates it quite a bit.

    Also since is it possible to widen the bandwidth to 100 Mhz just from this method? Are there any other tricks to lowering the Miller Effect? Please help! Also I cannot use any capacitor in my design because it has to work all the way from DC so anything that includes capacitors is out of the question.
  2. jcsd
  3. Jul 7, 2006 #2


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    I think you are a bit confused about what you should do with your dominant pole. Look at typical opamp datasheets for some clues. Where does a typical opamp have its dominant pole, and why? What are the implications of moving the dominant pole (and the second pole) around with respect to the unity gain phase margin?

    And since you will be using a small capacitance to place your dominant pole (even if it's the parasitic capacitance of a transistor), of course you can have capacitors in an amplifier that works to DC.

    In your project specs, you need to find out at what frequency you need the gain of 1000. Are they asking you to maintain a closed loop gain of 1000 all the way to 12MHz? That's asking a lot, especially if you are going to try to build this with discrete transistors. The advantage of monolithic silicon opamps is that you can use tiny transistors with tiny interconnect parasitic capacitances. When you lay the opamp design out on a discrete PCB, the parasitic capacitances kill your high frequency performance.

    And for your Miller effect question -- check out the cascode configuration.
  4. Jul 7, 2006 #3
    Yes I am very certain that they want a gain of 1000 from DC all the way to 12 Mhz. I think it can be done but is not "trivial" based on what my professor said. I have to keep the gain for each stage low while maintaining a very high bandwidth.

    The professor that gave me this project actually told me to do exactly what I said previously - i.e. have one stage that sets the dominant pole and the rest at a much higher frequency so it won't intefere with it. He suggested for me to use a cascode to set the dominant pole and get as much gain as possible while the other stages can be done with a CE.

    And I don't understand your questions about dominant pole. Can you please explain?
  5. Jul 7, 2006 #4


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    Most definitely not trivial. I wonder how you are supposed to test an amplifier with a gain of 1000. Put in 1mVpp and try to measure 1Vpp at the output? Put in 100uVpp and measure 100mVpp?

    Well, anyway, it sounds like a special amplifier application, not a general opamp design. What I'm more used to in general opamp design is placing the dominant pole at a lower frequency (using the Miller capacitance of the first diffamp stage), and placing the 2nd pole up near the unity gain crossover point, in order to have some reasonable phase margin at unity gain.

    But for high frequency amps, maybe things are done differently. It doesn't sound like you have to be unity gain stable, for example. You might check out some of the high speed amps at Maxim to see if you get any ideas. They mostly seem to use current feedback, for example:


    I still think that there will be some pretty serious practical problems with building a discrete amp with the specs you mention. Again, the parasitic capacitance of discrete transistor packages really limits how fast you can run them. And it's very hard to get well-match transistor pairs to make discrete diffamp stages with. And it's hard to keep each stage of the amp from talking to previous stages and causing oscillations. But maybe it can be done. I'd sure be interested in seeing the final designs of you and your classmates.
  6. Jul 9, 2006 #5
    yes, I am suppose to put 10 mVpp and try to measure 10 Vpp. My professor told me to try to set the dominant pole using the cascode amplifier and place it as the 2nd to last gain stage.

    Yes it's true besides having the required gain/bandwidth and the correct input and output impedance I don't need any other requirement. So whatever happens after 12 Mhz I can care less. It's for a project and those are pretty much all requirements I have to meet. No CMRR or any other requirements that would usually be important in such design.
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