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Capacitive Coupling Issue

  1. Aug 31, 2014 #1
    I have an FPGA demo board and on the GPIO I have attached a 4 x 3 membrane keypad. This keypad is simple, create a current on the column pins and look for a completed circuit on the row pins.

    http://iteadstudio.net/Wholesale/images/icons/3x4keypad.jpg [Broken]

    At the minute, I just having it driving a bunch of LEDs to indicate what has been pressed. I have written the VHDL code for this and it appears to be working fine.

    My problem is that if I bring my hand within 15cm of the keypad, the LEDs start to light up. So, I am coupling with the circuit and bridging the switches. I dropped the frequency from 2MHz to 1KHz to try to resolve it, but no luck. I can move my hand around the keypad and cause different LEDs to light up.

    Does anyone have a resolution for me?
    Last edited by a moderator: May 6, 2017
  2. jcsd
  3. Aug 31, 2014 #2
    If your membrane pad is the same as some I'm familiar with, when a button is pressed, it simply completes the circuit between a single X and a single Y line to signal which button is being pressed. With that, I assume you're interfacing by driving one X (or Y) line high at a time (scanning across the set), and sensing what line in the corresponding Y (or X) group goes high. That being said, your sense circuit might typically be CMOS which is very sensitive to induced voltages (including those from your hand). A simple pull-down resistor (about 1 to 10K) on each sense line should take care of that problem. I'm not sure what your talking about relative to the frequency. Is that the keypad scan frequency or the main clock frequency? If it's a matter of induced voltage, the scan frequency is pretty much irrelevant.
    Last edited: Aug 31, 2014
  4. Aug 31, 2014 #3
    The I/O standard is 3.3-V LVTTL and your assumption about the method employed is correct.

    Does the solution remain the same?

    Is there any way to predict this type of behaviour or standard formulas?
    Would changing the current strength or I/O standard help at all?
  5. Aug 31, 2014 #4
    I'm not that familiar with the LVTTL topology, but I think the same solution would apply. There really aren't any formulas - just experience with the behavior of sensitive inputs. It certainly won't cause any damage to apply the pull-down resistors to the sense lines so I would try that as a first step. It really should work once you remedy the induced voltages.

    It's also possible that your scan generator takes the lines low one-at-a-time. In that case, you would use pull-up resistors on the sense lines. The latter is actually the preferred method if it's a true TTL topology since the input to a TTL gate wants to source current (to ground) in order to see a LOW condition. You should be able to accomplish this through software, though it could be burdensome to make the change.

    Attached Files:

    Last edited: Aug 31, 2014
  6. Aug 31, 2014 #5
    Both actually, I'm not doing anything fancy. Initially, I thought the high frequency may be playing a role.
  7. Aug 31, 2014 #6
    Thanks for that solution, I will give it a shot tomorrow and let you know if it resolved it.
  8. Aug 31, 2014 #7
    Good Luck. Do let us know how it works out.
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